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    • 3. 发明授权
      US06725649B2 Control apparatus for a direct-injection, spark-ignition engine 失效
    • Control apparatus for a direct-injection, spark-ignition engine
    • 直喷式火花点火式发动机的控制装置
    • US06725649B2
    • 2004-04-27
    • US10235951
    • 2002-09-06
    • Hiroyuki Yamashita , Masashi Marubara , Hiroyuki Yoshida , Noriyuki Ohta
    • Hiroyuki Yamashita , Masashi Marubara , Hiroyuki Yoshida , Noriyuki Ohta
    • F01N300
    • F02D41/402 , F02B2075/125 , F02D41/024 , F02D41/3023 , Y02T10/123 , Y02T10/26 , Y02T10/44
    • A control apparatus for a direct-injection, spark-ignition engine including a temperature-condition detector for detecting a temperature condition of the engine catalyst, and a controller for controlling a fuel-injection operation. The controller controls the fuel injector to perform divided fuel injections of at least a leading fuel injection and a trailing fuel injection during a compression stroke prior to the ignition timing based upon a detection of the temperature condition in an inactivated state of the catalyst, the trailing fuel injection being performed at such a timing that its mixture concentrates adjacent to the spark plug at the ignition timing by way of high cylinder pressure during a late-stage of the compression stroke, the leading fuel injection being performed at such a timing that its mixture distributes around a mixture layer by the trailing fuel injection at the ignition timing, and a midpoint between an initiation of the leading fuel injection and an initiation of the trailing fuel injection being positioned within a period during a latter half of a compression stroke.
    • 一种用于直接喷射火花点火发动机的控制装置，包括用于检测发动机催化剂的温度状况的温度条件检测器和用于控制燃料喷射操作的控制器。 控制器控制燃料喷射器，以在点火正时之前的压缩行程期间基于在催化剂的失活状态下的温度条件的检测，进行至少前导燃料喷射和尾燃料喷射的分配燃料喷射，尾随 在压缩行程的后期阶段，通过高气缸压力在点火正时使其混合物在火花塞附近集中的燃料喷射进行燃料喷射，前进燃油喷射在其混合物 在点火正时通过尾燃料喷射分布在混合物层周围，并且在压缩冲程的后半段期间，在先导燃料喷射的开始和尾燃料喷射的开始位于一段时间内的中点。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5691937A Structure of split gate transistor for use in a non-volatile semiconductor memory and method of manufacturing such a split gate transistor 失效
    • Structure of split gate transistor for use in a non-volatile semiconductor memory and method of manufacturing such a split gate transistor
    • 用于非易失性半导体存储器的分离栅极晶体管的结构和制造这种分离栅极晶体管的方法
    • US5691937A
    • 1997-11-25
    • US701013
    • 1996-08-21
    • Noriyuki Ohta
    • Noriyuki Ohta
    • H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C16/04 , H01L29/68
    • H01L27/11521 , H01L27/115 , H01L29/42324
    • A non-volatile semiconductor memory is composed of split gate type memory cell transistors, each of which comprises a source region and a drain region formed at a principal surface of a semiconductor substrate, separately from each other to form a channel region between the source region and the drain region. This channel region is divided into a first channel region adjacent to the drain region and a second channel region adjacent to the source region. A first gate insulator film is formed on a surface of the first channel region, and a control gate electrode is formed on the first gate insulator film. An insulator layer is formed on the source region and the drain region, and a second gate insulator film is formed on an upper surface and a pair of opposite side surfaces of the control gate electrode and on a surface of the second channel region. A floating gate electrode is formed on the second gate insulator film to have opposite ends terminating on the insulator layer formed on the source region and the insulator layer formed on the drain region, respectively.
    • 非易失性半导体存储器由分离栅型存储单元晶体管组成，其中每个分离栅型存储单元晶体管分别形成在半导体衬底的主表面上的源极区和漏极区，以形成源极区之间的沟道区 和漏极区域。 该沟道区域被分成与漏极区域相邻的第一沟道区域和与源极区域相邻的第二沟道区域。 第一栅极绝缘膜形成在第一沟道区的表面上，在第一栅极绝缘膜上形成控制栅电极。 在源极区域和漏极区域上形成绝缘体层，并且在控制栅电极的上表面和一对相对的侧表面上以及在第二沟道区域的表面上形成第二栅绝缘膜。 浮置栅电极形成在第二栅极绝缘膜上，具有分别在形成于源极区域上的绝缘体层和形成于漏极区域上的绝缘体层的相对端。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5808940A Nonvolatile semiconductor memory 失效
    • Nonvolatile semiconductor memory
    • 非易失性半导体存储器
    • US5808940A
    • 1998-09-15
    • US828757
    • 1997-03-25
    • Noriyuki Ohta , Noriaki Kodama , Toshikatsu Jinbo
    • Noriyuki Ohta , Noriaki Kodama , Toshikatsu Jinbo
    • G11C17/00 , G11C16/02 , G11C16/06 , G11C16/30 , G11C16/04
    • G11C16/30
    • A nonvolatile semiconductor memory includes a cell array prepared by arranging erasable and programmable memory cell transistors in rows and columns, word lines arranged in correspondence with the respective rows of the cell array and connected to the control gates of the memory cell transistors, digit lines arranged in correspondence with the respective columns of the cell array and connected to the drains of the memory cell transistors, source lines connected to the sources of the memory cell transistors, and a source power supply circuit for applying a source voltage to the source lines in an erase operation. This memory erases by the source voltage data in the memory cell transistors in the rows and columns of the cell array. The source power supply circuit is a circuit including a first P-channel transistor which sets a current to be supplied to the source lines to a predetermined value in the erase operation in a range wherein the source voltage is lower than a predetermined potential, and a second P-channel transistor which sets the current to be supplied to the source lines so as to decrease faster than the current decreased by the characteristic of the first transistor with an increase in source voltage in a range wherein the source voltage is higher than the predetermined potential.
    • 非易失性半导体存储器包括通过以行和列排列可擦除可编程存储单元晶体管而制备的单元阵列，与单元阵列的各行相对应地布置并连接到存储单元晶体管的控制栅极的字线，布置的数字线 与电池阵列的各列对应并连接到存储单元晶体管的漏极，连接到存储单元晶体管的源极的源极线和用于将源极电压施加到源极线的源极电源电路 擦除操作。 该存储器由单元阵列的行和列中的存储单元晶体管中的源电压数据擦除。 源极电源电路是包括第一P沟道晶体管的电路，该第一P沟道晶体管在源极电压低于预定电位的范围内将要提供给源极线的电流设置在擦除操作中的预定值，并且 第二P沟道晶体管，其设置要提供给源极线的电流，以便在源极电压高于预定的范围内，随着源极电压的增加，电流降低得比第一晶体管的特性减小的电流快。 潜在。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5557123A Nonvolatile semiconductor memory device with shaped floating gate 失效
    • Nonvolatile semiconductor memory device with shaped floating gate
    • 具有形状浮动栅极的非易失性半导体存储器件
    • US5557123A
    • 1996-09-17
    • US319605
    • 1994-10-07
    • Noriyuki Ohta
    • Noriyuki Ohta
    • H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C11/34
    • H01L29/42324 , H01L27/115
    • A nonvolatile semiconductor memory device with improved writing characteristics. The memory device has memory cell transistors arranged in rows and columns. The memory cell transistors belonging to the same column share a source region and a drain region, and a channel region is disposed between the source and drain regions. The interval between the source and drain regions is the isolation width. Each of the memory cell transistors has a floating gate electrode disposed on the channel region with a first gate insulating film and a control gate electrode disposed on the floating gate electrode with a second gate insulating film. The floating gate electrode does not have a constant width and has a portion narrower than the isolation width which is free from the floating gate electrode. The narrower portion is typically formed as a constricted portion of the floating gate electrode.
    • 一种具有改进写入特性的非易失性半导体存储器件。 存储器件具有以行和列排列的存储单元晶体管。 属于同一列的存储单元晶体管共享源区和漏区，沟道区设置在源区和漏区之间。 源区和漏区之间的间隔是隔离宽度。 每个存储单元晶体管具有设置在具有第一栅极绝缘膜的沟道区上的浮置栅极和设置在具有第二栅极绝缘膜的浮置栅电极上的控制栅电极。 浮置栅电极不具有恒定的宽度，并且具有比不含浮栅电极的隔离宽度窄的部分。 较窄部分通常形成为浮栅电极的收缩部分。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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