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1. 发明授权

US5684315A Semiconductor memory device including memory cells each having an information storage capacitor component formed over control electrode of cell selecting transistor 失效
标题翻译：半导体存储器件包括存储单元，每个存储单元都具有形成在单元选择晶体管的控制电极上的信息存储电容器组件
公开(公告)号：US5684315A
公开(公告)日：1997-11-04
申请号：US362879
申请日：1994-12-23
申请人： Hiroyuki Uchiyama , Yoshiyuki Kaneko , Hiroki Soeda , Yasuhide Fujioka , Nozomu Matsuda , Motoko Sawamura
发明人： Hiroyuki Uchiyama , Yoshiyuki Kaneko , Hiroki Soeda , Yasuhide Fujioka , Nozomu Matsuda , Motoko Sawamura
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/10852 , H01L27/10808
摘要： A semiconductor memory device has memory cells provided at intersections between word line conductors and data line conductors. Each of the memory cells includes a cell selecting transistor and an information storage capacitor. The capacitor in each of the memory cells includes a first capacitor component formed over the control electrode of the transistor and a second capacitor component formed over a word line conductor which is adjacent to a word line conductor integral with the control electrode of the transistor. Each of the first and second capacitor components has a common electrode, a storage electrode and a dielectric film sandwiched therebetween, and the storage electrode is at a level higher than the common electrode in each of said first and second capacitor components. The storage electrodes of the first and second capacitor components are electrically connected with each other and with one of the semiconductor regions of the transistor. The other semiconductor region of the transistor is electrically connected with one of the data line conductors. Patterning of the storage electrodes of the first and second capacitor components is preferalbly effected by use of masks of a stripe pattern.
摘要翻译：半导体存储器件具有在字线导体和数据线导体之间的交叉点处设置的存储单元。每个存储单元包括单元选择晶体管和信息存储电容器。每个存储单元中的电容器包括形成在晶体管的控制电极上的第一电容器部件和形成在字线导体上的第二电容器部件，该字线导体与与晶体管的控制电极成一体的字线导体相邻。第一电容器部件和第二电容器部件中的每一个均具有公共电极，存储电极和夹在其间的电介质膜，并且在所述第一和第二电容器部件的每个中，所述存储电极处于比所述公共电极高的电平。第一和第二电容器部件的存储电极彼此电连接并且与晶体管的半导体区域中的一个电连接。晶体管的另一个半导体区域与数据线导体之一电连接。第一和第二电容器部件的存储电极的图案化优选地通过使用条纹图案的掩模来实现。

2. 发明授权

US5631182A Method of making a semiconductor memory circuit device 失效
标题翻译：制造半导体存储器电路器件的方法
公开(公告)号：US5631182A
公开(公告)日：1997-05-20
申请号：US327861
申请日：1994-10-18
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

3. 发明授权

US5237187A Semiconductor memory circuit device and method for fabricating same 失效
标题翻译：半导体存储器电路器件及其制造方法
公开(公告)号：US5237187A
公开(公告)日：1993-08-17
申请号：US799541
申请日：1991-11-27
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similarly, the first through third insulating films of the first region are correspondingly associated with the first through third insulating films of the second region, respectively.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，存在作为存储单元阵列区域的第一区域，第一 MISFET具有栅极电极和源极和漏极区域; 第一和第二电容器电极以及在第一绝缘膜上并在栅电极上方延伸的电介质膜; 设置在所述第二电容器电极上的第二绝缘膜; 介于所述第一绝缘膜和所述第一电容器电极之间的第三绝缘膜; 以及位于第二绝缘膜上的第一布线。在作为外围电路区域的器件的第二区域中，存在具有栅极电极和源极和漏极区域的第二MISFET，栅电极上的第一绝缘膜; 在第三绝缘膜上的第二绝缘膜，所述第三绝缘膜介于所述第一和第二绝缘膜之间; 以及在第二绝缘膜上的第二布线。第二布线由与形成第一布线的层相同的导体层形成。类似地，第一区域的第一至第三绝缘膜分别与第二区域的第一至第三绝缘膜相关联。

4. 发明授权

US6043118A Semiconductor memory circuit device and method for fabricating a semiconductor memory device circuit 失效
标题翻译：半导体存储器电路器件及半导体存储器件电路的制造方法
公开(公告)号：US6043118A
公开(公告)日：2000-03-28
申请号：US800018
申请日：1997-02-13
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

5. 发明授权

US5389558A Method of making a semiconductor memory circuit device 失效
标题翻译：制造半导体存储器电路器件的方法
公开(公告)号：US5389558A
公开(公告)日：1995-02-14
申请号：US104014
申请日：1993-08-10
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

6. 发明授权

US08183091B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08183091B2
公开(公告)日：2012-05-22
申请号：US12757364
申请日：2010-04-09
申请人： Hiroyuki Uchiyama , Hiraku Chakihara , Teruhisa Ichise , Michimoto Kaminaga
发明人： Hiroyuki Uchiyama , Hiraku Chakihara , Teruhisa Ichise , Michimoto Kaminaga
IPC分类号： H01L23/544 , H01L21/304
CPC分类号： H01L23/544 , G03F9/7076 , H01L21/30625 , H01L21/31053 , H01L21/76229 , H01L21/76819 , H01L21/78 , H01L22/34 , H01L23/585 , H01L27/0207 , H01L29/78 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.
摘要翻译：半导体IC包括形成在基板中的槽，用于限定形成在划线区域的第一虚拟区域和第二虚拟区域，以及形成在产品区域的第三虚拟区域和第四虚拟区域。第一虚拟区域的宽度大于第二和第三虚拟区域中的每一个的宽度，并且第四虚拟区域的宽度大于每个第三虚拟区域的宽度。在第一虚拟区域上形成用于光学图案识别的导体图案。第一虚拟区域形成在导体图案下方，使得沟槽不形成在导体图案之下。第二虚拟区域在划刻区域处以预定间隔彼此间隔开，并且第三虚拟区域在产品区域处彼此间隔开预定间隔。

7. 发明授权

US08013373B2 Semiconductor device having MOS-transistor formed on semiconductor substrate and method for manufacturing thereof 有权
标题翻译：具有形成在半导体衬底上的MOS晶体管的半导体器件及其制造方法
公开(公告)号：US08013373B2
公开(公告)日：2011-09-06
申请号：US12361117
申请日：2009-01-28
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L21/823437 , H01L27/10814 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion layer has been formed. A first device isolation area with a STI structure for separating the diffusion layers that function as a source/drain area is formed on the surface of the substrate. A second device isolation area with the STI structure for separating channel areas of the MOS transistors adjacent to each other is formed in a layer that is lower than a layer that has the first device isolation area.
摘要翻译：半导体器件包括依次布置在衬底的平面方向上的MOS晶体管，其中用于将栅电极彼此连接的栅电极和布线部分被注入到低于衬底表面的层中，其中，扩散层已经形成。在基板的表面上形成具有用于分离用作源极/漏极区域的扩散层的STI结构的第一器件隔离区域。具有用于分离相邻的MOS晶体管的沟道区域的STI结构的第二器件隔离区域形成在低于具有第一器件隔离区域的层的层中。

8. 发明申请

US20110081655A1 NUCLEIC ACID ANALYZING DEVICE AND NUCLEIC ACID ANALYZER 有权
标题翻译：核酸分析装置和核酸分析仪
公开(公告)号：US20110081655A1
公开(公告)日：2011-04-07
申请号：US12997469
申请日：2009-05-13
申请人： Masatoshi Narahara , Toshiro Saito , Naoshi Itabashi , Jiro Yamamoto , Hiroyuki Uchiyama
发明人： Masatoshi Narahara , Toshiro Saito , Naoshi Itabashi , Jiro Yamamoto , Hiroyuki Uchiyama
IPC分类号： C12Q1/68 , C12M1/34
CPC分类号： G01N21/648
摘要： An object of the present invention relates to distinguishing, from a fluorophore of an unreacted substrate, a single fluorophore attached to a nucleotide that is incorporated into a probe by a nucleic acid synthesis. The present invention relates to a nucleic acid analyzing device that analyzes a nucleic acid in sample by fluorescence, wherein a localized surface plasmon is generated by illumination, and a probe for analyzing the nucleic acid in the sample is on the site where the surface plasmon is generated. According to the present invention, since it is possible to efficiently produce fluorescence intensifying effects due to the surface plasmon and to immobilize the probe to a region within the reach of the fluorescence intensifying effects, it becomes possible to measure a nucleic acid synthesis without removing unreacted nucleotide to which fluorophores are attached.
摘要翻译：本发明的目的在于从未反应的底物的荧光团区分与通过核酸合成并入探针中的核苷酸连接的单个荧光团。本发明涉及通过荧光分析样品中的核酸的核酸分析装置，其中通过照射产生局部表面等离子体激元，并且用于分析样品中的核酸的探针位于表面等离子体为生成。根据本发明，由于可以有效地产生由于表面等离子体激元引起的荧光增强作用并且将探针固定在荧光增强作用范围内的区域，因此可以测量核酸合成而不去除未反应的附着有荧光团的核苷酸。

9. 发明授权

US07816702B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07816702B2
公开(公告)日：2010-10-19
申请号：US12245077
申请日：2008-10-03
申请人： Shinichi Saito , Masahiro Aoki , Hiroyuki Uchiyama , Hideo Arimoto , Noriyuki Sakuma , Jiro Yamamoto
发明人： Shinichi Saito , Masahiro Aoki , Hiroyuki Uchiyama , Hideo Arimoto , Noriyuki Sakuma , Jiro Yamamoto
IPC分类号： H01L33/00
CPC分类号： H01S5/12 , B82Y20/00 , H01S5/0424 , H01S5/0425 , H01S5/1237 , H01S5/125 , H01S5/18341 , H01S5/3004 , H01S5/3427 , H01S2301/176 , H01S2302/00
摘要： There are a silicon laser device having a IV-group semiconductor such as silicon or germanium equivalent to the silicon as a basic constituent element on a substrate made of the silicon, and the like by a method capable of easily forming the silicon laser device by using a general silicon process, and a manufacturing method thereof. The silicon laser device is an ultrathin silicon laser that includes a first electrode unit injecting electrons, a second electrode unit injecting holes, a light emitting unit electrically connected to the first electrode unit and the second electrode unit, wherein the light emitting unit is made of single-crystal silicon and has a first surface (top surface) and a second surface (bottom surface) opposed to the first surface, a waveguide made of a first dielectric, which is disposed in the vicinity of the light emitting unit, by setting surface directions of the first and second surfaces as a surface (100) and thinning a thickness of the light emitting unit in a direction perpendicular to the first and second surfaces, and a mirror formed by alternately adjoining the first dielectric and a second dielectric.
摘要翻译：存在具有诸如硅等离子体的硅组合半导体的硅激光器装置，其等同于由硅制成的衬底上作为基本构成元件的硅等，通过使用能够容易地形成硅激光器件的方法，通用硅工艺及其制造方法。硅激光器件是一种超薄硅激光器，其包括注入电子的第一电极单元，注入空穴的第二电极单元，与第一电极单元和第二电极单元电连接的发光单元，其中发光单元由单晶硅，并且具有与第一表面相对的第一表面（顶表面）和第二表面（底表面），通过设置在发光单元附近的由第一电介质制成的波导第一表面和第二表面的方向作为表面（100），并且在垂直于第一和第二表面的方向上减薄发光单元的厚度，以及通过交替地邻接第一电介质和第二电介质而形成的反射镜。

10. 发明申请

US20100237397A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100237397A1
公开(公告)日：2010-09-23
申请号：US12659563
申请日：2010-03-12
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： To provide an active region having first and second diffusion layers positioned at both sides of a gate trench and a third diffusion layer formed on a bottom surface of the gate trench, first and second memory elements connected to the first and second diffusion layers, respectively, a bit line connected to the third diffusion layer, a first gate electrode that covers a first side surface of the gate trench via a gate dielectric film and forms a channel between the first diffusion layer and the third diffusion layer, and a second gate electrode that covers a second side surface of the gate trench via a gate dielectric film and forms a channel between the second diffusion layer and the third diffusion layer. According to the present invention, because separate transistors are formed on both side surfaces of a gate trench, two times of conventional integration can be achieved.
摘要翻译：为了提供具有位于栅极沟槽的两侧的第一和第二扩散层和形成在栅极沟槽的底表面上的第三扩散层的有源区，分别连接到第一和第二扩散层的第一和第二存储元件，连接到所述第三扩散层的位线，经由栅极电介质膜覆盖所述栅极沟槽的第一侧表面并在所述第一扩散层和所述第三扩散层之间形成沟道的第一栅电极，以及第二栅电极，经由栅极电介质膜覆盖栅极沟槽的第二侧表面，并在第二扩散层和第三扩散层之间形成通道。根据本发明，由于在栅极沟槽的两个侧表面上形成分离的晶体管，所以可以实现两次常规集成。

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