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1. 发明授权

US06944081B2 Semiconductor storage and its refreshing method 失效
标题翻译：半导体存储及其刷新方法
公开(公告)号：US06944081B2
公开(公告)日：2005-09-13
申请号：US10363298
申请日：2001-08-30
申请人： Hiroyuki Takahashi , Atsushi Nakagawa , Yoshiyuki Katou , Hideo Inaba , Noriaki Komatsu , Takuya Hirota , Masahiro Yoshida
发明人： Hiroyuki Takahashi , Atsushi Nakagawa , Yoshiyuki Katou , Hideo Inaba , Noriaki Komatsu , Takuya Hirota , Masahiro Yoshida
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.
摘要翻译：提供能够进一步降低刷新操作的功耗的半导体存储器件。单元阵列S 0，S 1被分成四个块B 0〜B 3和B 10〜B 13。在通常的读/写操作中，通过指定字线的地址数据，选择单元阵列中的一个，并且在所选择的单元阵列中选择一个块，并且在所选块中还选择一个字线。在刷新操作中，选择单元阵列之一，同时刷新所选单元阵列中的四个块。也就是说，从四个块中的每一个中选择相应的一个字线，并且与多个单元阵列刷新时相比，刷新所选择的字线，从而降低功耗。

2. 发明申请

US20050047239A1 Semiconductor storage device and refresh control method thereof 有权
标题翻译：半导体存储装置及其刷新控制方法
公开(公告)号：US20050047239A1
公开(公告)日：2005-03-03
申请号：US10500400
申请日：2002-12-25
申请人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
发明人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40603 , G11C11/406
摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.
摘要翻译：通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和输出使能信号REN。当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后，当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变成“H”电平，刷新请求被输入到输出刷新脉冲发生器电路170和刷新使能信号RERF。

3. 发明授权

US07006401B2 Semiconductor storage device and refresh control method thereof 有权
标题翻译：半导体存储装置及其刷新控制方法
公开(公告)号：US07006401B2
公开(公告)日：2006-02-28
申请号：US10500400
申请日：2002-12-25
申请人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
发明人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C11/406
摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.
摘要翻译：通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和输出使能信号REN。当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后，当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变为“H”电平，刷新请求被输入到刷新脉冲发生器电路170，并且输出刷新使能信号RERF。

4. 发明授权

US07035154B2 Semiconductor memory device and its test method as well as test circuit 失效
标题翻译：半导体存储器件及其测试方法以及测试电路
公开(公告)号：US07035154B2
公开(公告)日：2006-04-25
申请号：US10362891
申请日：2001-08-30
申请人： Hiroyuki Takahashi , Yoshiyuki Katou , Hideo Inaba , Shouzou Uchida , Masatoshi Sonoda
发明人： Hiroyuki Takahashi , Yoshiyuki Katou , Hideo Inaba , Shouzou Uchida , Masatoshi Sonoda
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/12 , G11C29/46
摘要： The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array 30. Then, a test signal TE1 is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit 51. A first address for test is applied to an address terminal 21, whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal 21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array 30 are checked to decide the presence or absence of any abnormality.
摘要翻译：本发明提供一种能够在地址组合中的最坏情况下检查操作的半导体存储器件及其制造方法。用于测试的具体数据被写入存储单元阵列30.然后，将测试信号TE 1设置为“1”以将设备设置在测试模式中。然后将用于测试的刷新地址存储在数据存储电路51中。用于测试的第一地址被应用于地址终端21，由此基于用于测试的第一地址来完成正常的读取或写入操作。用于测试的第二地址被应用于地址终端21，由此基于用于测试的地址来完成刷新操作，并且随后基于第二测试地址来完成另一个正常的读取或写入操作。对存储单元阵列30的数据进行检查，判定有无异常。

5. 发明授权

US07466609B2 Semiconductor memory device and semiconductor memory device control method 有权
标题翻译：半导体存储器件和半导体存储器件控制方法
公开(公告)号：US07466609B2
公开(公告)日：2008-12-16
申请号：US11882230
申请日：2007-07-31
申请人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
IPC分类号： G11C7/22 , G11C8/18 , G11C8/08 , G11C5/14 , G11C7/12
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译：电池芯单元及其外围电路由相对低压的电源驱动。提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。读出放大器将位线的较高电压电平放大到电源电压。然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟，降低所提供的电源电压。

6. 发明申请

US20080056031A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20080056031A1
公开(公告)日：2008-03-06
申请号：US11907442
申请日：2007-10-12
申请人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
IPC分类号： G11C11/4074 , G11C11/4063 , G11C7/00
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译：电池芯单元及其外围电路由相对低压的电源驱动。提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。读出放大器将位线的较高电压电平放大到电源电压。然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟，降低所提供的电源电压。

7. 发明申请

US20070280025A1 Semiconductor memory device and semiconductor memory device control method 有权
标题翻译：半导体存储器件和半导体存储器件控制方法
公开(公告)号：US20070280025A1
公开(公告)日：2007-12-06
申请号：US11882230
申请日：2007-07-31
申请人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译：电池芯单元及其外围电路由相对低压的电源驱动。提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。读出放大器将位线的较高电压电平放大到电源电压。然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟，降低所提供的电源电压。

8. 发明授权

US07663945B2 Semiconductor memory with a delay circuit 有权
标题翻译：具有延迟电路的半导体存储器
公开(公告)号：US07663945B2
公开(公告)日：2010-02-16
申请号：US11907442
申请日：2007-10-12
申请人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
IPC分类号： G11C7/22 , G11C8/18
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译：电池芯单元及其外围电路由相对低压的电源驱动。提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。读出放大器将位线的较高电压电平放大到电源电压。然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟，降低所提供的电源电压。

9. 发明授权

US07301830B2 Semiconductor memory device and semiconductor device and semiconductor memory device control method 有权
标题翻译：半导体存储器件和半导体器件及半导体存储器件控制方法
公开(公告)号：US07301830B2
公开(公告)日：2007-11-27
申请号：US10507117
申请日：2004-09-10
申请人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
IPC分类号： G11C11/4074 , G11C11/4076 , G11C11/4063 , G11C7/22 , G11C8/18 , G11C8/08 , G11C7/12
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译：电池芯单元及其外围电路由相对低压的电源驱动。提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。读出放大器将位线的较高电压电平放大到电源电压。然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟，降低所提供的电源电压。

10. 发明申请

US20050237848A1 Semiconductor memory device and semiconductor device and semiconductor memory device control method 有权
标题翻译：半导体存储器件和半导体器件及半导体存储器件控制方法
公开(公告)号：US20050237848A1
公开(公告)日：2005-10-27
申请号：US10507117
申请日：2004-09-10
申请人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Takuya Hirota , Atsushi Nakagawa
IPC分类号： H01L21/822 , G11C11/407 , G11C11/4074 , G11C11/4076 , H01L27/04 , H03K5/14 , G11C8/02
CPC分类号： G11C5/145 , G11C5/147 , G11C11/4074 , G11C11/4085 , G11C2207/2227 , H03K5/133
摘要： A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.
摘要翻译：电池芯单元及其外围电路由相对低压的电源驱动。提供不依赖于电源电压的恒定电压作为提供给单元芯单元的字线的控制信号的升压电压（VBOOST）。读出放大器将位线的较高电压电平放大到电源电压。然后，用于产生用于定义从外围电路到小区核心单元的控制信号的转变定时和/或脉冲宽度的信号的电路使用具有延迟时间减小的特性的延迟电路来执行信号延迟，降低所提供的电源电压。

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