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1. 发明专利

JP2008256343A Mixture combustion device for hydrophilic liquid and combustion method 审中-公开
标题翻译：用于液体液体和燃烧方法的混合燃烧装置
公开(公告)号：JP2008256343A
公开(公告)日：2008-10-23
申请号：JP2007123949
申请日：2007-04-05
申请人： ▲高▼野 ▲将▼ , Susumu Takano
发明人： TAKANO SUSUMU
IPC分类号： F23G7/04
摘要： PROBLEM TO BE SOLVED: To provide a combustion device for hardly combustible liquid, simply constructed and installed to actualize stable combustion when burning a mixture of hardly combustible liquid mainly containing polyhydric alcohol such as glycerin and fuel, and to provide a combustion method.
SOLUTION: The mixture combustion device for hydrophilic liquid comprises a line for mixing the hydrophilic liquid and fuel at the last minute and supplying them to a swirl type injection nozzle, and an air supply line. Herein, fire flames are released into a combustion furnace. The combustion method uses the same.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种几乎不易燃液体的燃烧装置，在燃烧主要含有多元醇如甘油和燃料的几乎不易燃的液体的混合物时，简单地构造和安装以实现稳定的燃烧，并提供燃烧方法。解决方案：用于亲水液体的混合燃烧装置包括最后一分钟用于混合亲水性液体和燃料的管线，并将其供给到旋流式喷嘴和空气供应管线。在这里，火焰被释放到燃烧炉中。燃烧方法使用相同。版权所有（C）2009，JPO＆INPIT

2. 发明授权

US08760943B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US08760943B2
公开(公告)日：2014-06-24
申请号：US13599730
申请日：2012-08-30
申请人： Toshihiko Funaki , Toshiharu Okamoto , Muneaki Matsushige , Kenichi Kuboyama , Shuuichi Senou , Susumu Takano
发明人： Toshihiko Funaki , Toshiharu Okamoto , Muneaki Matsushige , Kenichi Kuboyama , Shuuichi Senou , Susumu Takano
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00 , G11C8/06 , G11C8/12 , G11C11/4096
CPC分类号： G11C7/1048 , G11C7/00 , G11C7/10 , G11C7/1006 , G11C8/12 , G11C11/4096 , H03K5/15006
摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.
摘要翻译：根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，通过第一数据总线连接到第一总线接口电路的第一存储器核心，第一存储器核心连接到第一存取控制信号从第一总线接口电路输出的第二存储器核心，通过第二数据总线连接到第二总线接口电路的第二存储器核心，以及选择性地将第一存取控制信号和第二存取控制信号输出的第二存取控制信号第二总线接口电路到第二存储器核心。

3. 发明申请

US20050265086A1 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US20050265086A1
公开(公告)日：2005-12-01
申请号：US11136484
申请日：2005-05-25
申请人： Susumu Takano , Hiroyuki Takahashi
发明人： Susumu Takano , Hiroyuki Takahashi
IPC分类号： G11C5/00 , G11C5/06 , G11C7/10 , G11C7/22
CPC分类号： G11C7/106 , G11C5/066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C2207/107
摘要： Disclosed is a semiconductor storage device which has a shared address/data terminal that shares an address terminal and a data terminal. In a latency period extending from receipt of an access command to a cell array to input or output of data, which corresponds to an access command, from the shared address/data terminal, pipeline control is performed in response to receipt of at least one other access command. Input or output of data from the shared address/data terminal corresponding to the other access commands is performed successively following data that corresponds to the initial access command.
摘要翻译：公开了具有共享地址/数据终端的半导体存储装置，共享地址端子和数据端子。在从接收到访问命令到单元阵列延伸到从共享地址/数据终端对应于访问命令的数据的输入或输出的延迟期间中，响应于至少一个其他的接收执行流水线控制访问命令。与对应于其他访问命令的来自共享地址/数据终端的数据的输入或输出连续地按照与初始访问命令对应的数据执行。

4. 发明授权

US06315459B1 Synthetic resin cage for roller bearing 有权
标题翻译：滚子轴承合成树脂保持架
公开(公告)号：US06315459B1
公开(公告)日：2001-11-13
申请号：US09164676
申请日：1998-10-01
申请人： Susumu Takano , Yukio Ohura
发明人： Susumu Takano , Yukio Ohura
IPC分类号： F16C3346
CPC分类号： F16C33/4605 , F16C19/26 , F16C19/28 , F16C33/46 , F16C33/467 , F16C33/491 , F16C33/498 , F16C2240/40
摘要： A synthetic resin cage for use in a bearing is provide to have a circular ring section and a column section with a plurality of columns, wherein only the base ends of the columns (4) are continued to the circular rig section (5) with the tip ends of the columns (4) being free, and some of the columns (4) have their tip ends connected to each other within a circumferential connecting frame portion (8), and e.g. part of the connecting frame portion (8) aces the end face of the rollers (6) to prevent the cage (1a) from dropping out of the bearing.
摘要翻译：提供一种用于轴承的合成树脂保持架具有圆形环段和具有多列的柱段，其中只有柱（4）的基端部连续到圆形钻机段（5），其中列（4）的末端是自由的，并且一些列（4）的顶端在圆周连接框架部分（8）内彼此连接，并且例如连接框架部分（8）的一部分与滚子（6）的端面相接触，以防止保持架（1a）从轴承中脱出。

5. 发明授权

US5251498A Device for measuring the physical state of an object 失效
标题翻译：用于测量物体的物理状态的装置
公开(公告)号：US5251498A
公开(公告)日：1993-10-12
申请号：US857431
申请日：1992-03-25
申请人： Eiji Nakatsukasa , Ippey Yamauchi , Susumu Takano
发明人： Eiji Nakatsukasa , Ippey Yamauchi , Susumu Takano
IPC分类号： G01B5/02 , G01B7/16 , G01D21/02 , G01G19/18 , G01G19/52 , B60K17/354
CPC分类号： G01B7/16 , G01D21/02 , G01G19/18
摘要： To solve the problem that the prior device has a difficulty in performing accurate measurement of weight or dimension of a work which is placed in a furnace, the invention provides a device for measuring the physical state of the work under high temperature conditions such as a sintering furnace, which comprises: a frame for holding a work; a base on which the frame is placed; a probe having an end portion disposed for relative movement between the work and the frame; a step motor for driving the probe so that the end portion of the probe moves between the work and the frame and also lifts the frame together with the work away from the base; a microcomputer which acts together with a magnetic scale and a load cell to send a control signal to the step motor, thereby detecting a displacement of the probe and a load imposed on the probe.

6. 发明授权

US07924651B2 Semiconductor storage device and resetting method for a semiconductor storage device 有权
标题翻译：半导体存储装置的半导体存储装置及复位方法
公开(公告)号：US07924651B2
公开(公告)日：2011-04-12
申请号：US12314060
申请日：2008-12-03
申请人： Susumu Takano
发明人： Susumu Takano
IPC分类号： G11C8/00
CPC分类号： G11C7/1045 , G11C7/20
摘要： An exemplary aspect of an embodiment of the present invention is a semiconductor storage device including a power-on reset generator that outputs a first reset signal in accordance with a level of a power supply voltage, a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin, an MRS controller that outputs a mode reset signal (MRSPON signal) in accordance with the mode set information, and a reset circuit that outputs a second reset signal initializing each circuit of an operation control section in accordance with the mode reset signal and the first reset signal.
摘要翻译：本发明的实施例的一个示例性方面是一种半导体存储装置，包括：上电复位发生器，其根据电源电压的电平输出第一复位信号;命令解码器，其移动到模式设定状态根据来自地址引脚的命令输出模式设定信息，根据模式设定信息输出模式复位信号（MRSPON信号）的MRS控制器输出模式组信息;以及复位电路，输出根据模式复位信号和第一复位信号初始化运算控制部分的每个电路的第二复位信号。

7. 发明申请

US20110007593A1 Semiconductor memory device and access method 失效
标题翻译：半导体存储器件和存取方法
公开(公告)号：US20110007593A1
公开(公告)日：2011-01-13
申请号：US12801860
申请日：2010-06-29
申请人： Susumu Takano
发明人： Susumu Takano
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C2211/4061
摘要： A semiconductor memory device includes a memory comprising a plurality of banks; an input section configured to input an address of a bank address, a row address and a column address; and a command generating circuit configured to issue one of a read command, a write command, and a refresh command based on to an input signal. A control section selects a selection bank from the plurality of banks based on the bank address when the read command or the write command is issued from the command generating circuit, performs a read operation or a write operation on the selection bank based on the row address and the column address, and performs a refresh operation on the selection bank when the refresh command is issued immediately after the read command or the write command.
摘要翻译：一种半导体存储器件，包括：存储器，包括多个存储体; 输入部，被配置为输入库地址的地址，行地址和列地址; 以及命令生成电路，被配置为基于输入信号发出读取命令，写入命令和刷新命令之一。当从命令发生电路发出读取命令或写入命令时，控制部分基于存储体地址从多个存储体中选择一个选择存储体，基于行地址对选择存储体执行读取操作或写入操作并且在读取命令或写入命令之后立即发出刷新命令时，对选择组执行刷新操作。

8. 发明授权

US07447109B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US07447109B2
公开(公告)日：2008-11-04
申请号：US11136484
申请日：2005-05-25
申请人： Susumu Takano , Hiroyuki Takahashi
发明人： Susumu Takano , Hiroyuki Takahashi
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C7/106 , G11C5/066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C2207/107
摘要： Disclosed is a semiconductor storage device which has a shared address/data terminal that shares an address terminal and a data terminal. In a latency period extending from receipt of an access command to a cell array to input or output of data, which corresponds to an access command, from the shared address/data terminal, pipeline control is performed in response to receipt of at least one other access command. Input or output of data from the shared address/data terminal corresponding to the other access commands is performed successively following data that corresponds to the initial access command.
摘要翻译：公开了具有共享地址/数据终端的半导体存储装置，共享地址端子和数据端子。在从接收到访问命令到单元阵列延伸到从共享地址/数据终端对应于访问命令的数据的输入或输出的延迟期间中，响应于至少一个其他的接收执行流水线控制访问命令。与对应于其他访问命令的来自共享地址/数据终端的数据的输入或输出连续地按照与初始访问命令对应的数据执行。

9. 发明授权

US06834004B2 Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout 失效
公开(公告)号：US06834004B2
公开(公告)日：2004-12-21
申请号：US10357752
申请日：2003-02-04
申请人： Susumu Takano , Hiroyuki Takahashi , Minoru Nizaka , Tomohiro Kitano
发明人： Susumu Takano , Hiroyuki Takahashi , Minoru Nizaka , Tomohiro Kitano
IPC分类号： G11C502
CPC分类号： H03K19/0948
摘要： A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

10. 发明授权

US06545892B2 Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout 有权
标题翻译：具有逻辑电路的半导体集成电路包括具有较低阈值电压值和改进的图案布局的晶体管
公开(公告)号：US06545892B2
公开(公告)日：2003-04-08
申请号：US09741304
申请日：2000-12-19
申请人： Susumu Takano , Hiroyuki Takahashi , Minoru Nizaka , Tomohiro Kitano
发明人： Susumu Takano , Hiroyuki Takahashi , Minoru Nizaka , Tomohiro Kitano
IPC分类号： G11C502
CPC分类号： H03K19/0948
摘要： A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.
摘要翻译：公开了一种包括逻辑电路的半导体集成电路，其中可以减小解码器面积并且具有减小整个芯片尺寸的效果。在逻辑电路中包括的MOS FET中，通过输出端子提供电荷的MOS FET以外的阈值电压值低于供给电荷的MOS FET的阈值电压值。每个MOS FET的栅极宽度的方向垂直于存储单元区域中字线延伸的方向，并且所有MOS FET在与字线延伸的方向垂直的方向上对准。

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