专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07035154B2 Semiconductor memory device and its test method as well as test circuit 失效
标题翻译：半导体存储器件及其测试方法以及测试电路
公开(公告)号：US07035154B2
公开(公告)日：2006-04-25
申请号：US10362891
申请日：2001-08-30
申请人： Hiroyuki Takahashi , Yoshiyuki Katou , Hideo Inaba , Shouzou Uchida , Masatoshi Sonoda
发明人： Hiroyuki Takahashi , Yoshiyuki Katou , Hideo Inaba , Shouzou Uchida , Masatoshi Sonoda
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/12 , G11C29/46
摘要： The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array 30. Then, a test signal TE1 is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit 51. A first address for test is applied to an address terminal 21, whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal 21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array 30 are checked to decide the presence or absence of any abnormality.
摘要翻译：本发明提供一种能够在地址组合中的最坏情况下检查操作的半导体存储器件及其制造方法。用于测试的具体数据被写入存储单元阵列30.然后，将测试信号TE 1设置为“1”以将设备设置在测试模式中。然后将用于测试的刷新地址存储在数据存储电路51中。用于测试的第一地址被应用于地址终端21，由此基于用于测试的第一地址来完成正常的读取或写入操作。用于测试的第二地址被应用于地址终端21，由此基于用于测试的地址来完成刷新操作，并且随后基于第二测试地址来完成另一个正常的读取或写入操作。对存储单元阵列30的数据进行检查，判定有无异常。

2. 发明授权

US06876592B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06876592B2
公开(公告)日：2005-04-05
申请号：US10220951
申请日：2001-03-07
申请人： Hiroyuki Takahashi , Hideo Inaba , Masatoshi Sonoda , Yoshiyuki Kato , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Hideo Inaba , Masatoshi Sonoda , Yoshiyuki Kato , Atsushi Nakagawa
IPC分类号： G11C11/403 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/408 , G11C29/04 , G11C7/00
CPC分类号： G11C11/406 , G11C11/4087
摘要： A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq).
摘要翻译：提供能够加速地址访问和缩短周期时间的半导体存储器件。第一地址解码器（2）和第一刷新地址解码器（5）分别解码从半导体存储器件外部提供的外部地址（Xn）和在半导体存储器件内用于刷新的刷新地址（RXn）。复用器（8）根据外部地址发送信号（EXTR）和刷新地址发送（EXTR），选择外部地址侧解码信号（XnDm）或刷新地址侧解码信号（XnRm），并输出作为解码信号（XnMm）的信号信号（RFTR），使得在一个存储器周期内连续地执行刷新操作和读/写操作。字驱动器（10）然后解码用多路复用器（8）等选择的解码信号（XnMm，XpMq），并激活字线（WLmq）。

3. 发明授权

US06646956B2 One-shot signal generating circuit 有权
标题翻译：单触发信号发生电路
公开(公告)号：US06646956B2
公开(公告)日：2003-11-11
申请号：US10221249
申请日：2002-09-10
申请人： Hiroyuki Takahashi , Hideo Inaba , Masatoshi Sonoda
发明人： Hiroyuki Takahashi , Hideo Inaba , Masatoshi Sonoda
IPC分类号： G11C800
CPC分类号： H03K5/1534 , G11C8/18 , H03K2005/00293
摘要： A one-shot signal generation circuit is provided which makes it easy to adjust pulse width and to deal with variation of skew of an ATD signal, and can reduce chip area. A timing determination section (100) is reset by an edge of a first detected signal among a plurality of address transition detection signals (ATD signals) which have arrived within the skew period of an address signal, measures a first predetermined time by taking an edge of a second detected signal as start instant, and outputs a signal DST which reflects the result of this measurement. A timing determination section (110) measures a second predetermined time by taking an edge of the first detected signal as start instant, and outputs a signal PG which reflects the result of this measurement. An LC generation circuit (14) outputs a one-shot signal (LC) whose start instant is determined by the signal PG and whose end instant is determined by the signal DST.
摘要翻译：提供了一个单触发信号发生电路，可以方便的调整脉冲宽度并应对ATD信号的偏斜变化，并可以减少芯片面积。定时确定部分（100）由在地址信号的歪斜时段内到达的多个地址转换检测信号（ATD信号）中的第一检测信号的边沿复位，通过取边缘来测量第一预定时间的第二检测信号作为开始时刻，并且输出反映该测量结果的信号DST。定时确定部分（110）通过将第一检测信号的边缘作为开始时刻来测量第二预定时间，并且输出反映该测量结果的信号PG。 LC生成电路（14）输出由信号PG确定开始时刻的单触发信号（LC），并且由信号DST确定其结束时刻。

4. 发明授权

US06714479B2 Semiconductor memory and control method 有权
标题翻译：半导体存储器和控制方法
公开(公告)号：US06714479B2
公开(公告)日：2004-03-30
申请号：US10333935
申请日：2003-01-23
申请人： Hiroyuki Takahashi , Masatoshi Sonoda
发明人： Hiroyuki Takahashi , Masatoshi Sonoda
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C8/18 , G11C11/406 , G11C11/408
摘要： The present invention provides a semiconductor memory device and control method capable of effectively suppressing the generation of operating current originating in noise of address signals provided from the outside without impairing the operating speed during reading and writing. This semiconductor memory device is provided with a filter circuit (102) for removing noise contained in address signals provided from the outside, a circuit system containing an ATD circuit (311) for generating a first address transition detection signal (&phgr;ATD1) by detecting a change in an address signal prior to passing through the filter circuit (102), and a circuit system containing an ATD circuit (321) for generating a second address transition detection signal (&phgr;ATD2) by detecting a change in an address signal after passing through the filter circuit (102). Refresh operation is controlled by first address transition detection signal (&phgr;ATD1), while read/write operation is controlled by second address transition detection signal (&phgr;ATD2). As a result, only the refresh operation is performed in the case noise has been generated, and the generation of operating current is effectively suppressed.
摘要翻译：本发明提供一种半导体存储器件和控制方法，其能够有效地抑制由外部提供的地址信号的噪声产生，而不损害读取和写入期间的操作速度。该半导体存储装置设置有用于去除从外部提供的地址信号中包含的噪声的滤波电路（102），包含用于通过检测变化来产生第一地址转换检测信号（phiATD1）的ATD电路（311）的电路系统在通过滤波器电路（102）之前的地址信号中，以及包含ATD电路（321）的电路系统，用于通过检测通过滤波器之后的地址信号的变化来产生第二地址转换检测信号（phiATD2）电路（102）。刷新操作由第一地址转换检测信号（phiATD1）控制，而读/写操作由第二地址转换检测信号（phiATD2）控制。结果，在产生噪声的情况下仅执行刷新操作，并且有效地抑制了工作电流的产生。

5. 发明授权

US07361967B2 Semiconductor device with fuse wires and connection wires 有权
标题翻译：具有保险丝和连接线的半导体器件
公开(公告)号：US07361967B2
公开(公告)日：2008-04-22
申请号：US11050708
申请日：2005-02-07
申请人： Hiroyuki Takahashi , Masayuki Yanagisawa , Masatoshi Sonoda , Yoshinori Ueno
发明人： Hiroyuki Takahashi , Masayuki Yanagisawa , Masatoshi Sonoda , Yoshinori Ueno
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L21/268 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.
摘要翻译：一种半导体器件，其中对应于多个熔丝的返回线集中地布置在相同的区域中。此外，返回线布置成多层。这种布置形成了在熔丝之间不设置返回布线的区域，从而允许以最小布线间距布置熔丝。或者，半导体器件可以包括分别布置在多个级中的熔丝串和用于分别向多个级中的熔丝串提供信号的多个连接线，其中用于其它熔丝串的连接线布置在相邻的保险丝串。

6. 发明授权

US07162657B2 Semiconductor storage device and controlling method therefor 有权
标题翻译：半导体存储装置及其控制方法
公开(公告)号：US07162657B2
公开(公告)日：2007-01-09
申请号：US10639716
申请日：2003-08-12
申请人： Hiroyuki Takahashi , Yuuji Matsui , Masatoshi Sonoda , Yosiyuki Kato
发明人： Hiroyuki Takahashi , Yuuji Matsui , Masatoshi Sonoda , Yosiyuki Kato
IPC分类号： G06F1/12
CPC分类号： G11C11/419
摘要： A semiconductor storage device includes a circuit receiving a command signal for generating a read control signal (RPB) based on the transition of a clock signal CLK and a circuit receiving the command signal for generating a write control signal (WPB) based on the transition of the clock signal CLK. The read cycle in which decoding of an address, selection of a word line and activation of a sense amplifier are executed based on the read control signal to read cell data, and the write cycle in which decoding of an address, selection of a word line and activation of a write amplifier are executed based on the write control signal and bit line pre-charging is also carried out, are carried out alternately. The sense period of the read cycle is overlapped with the decoding period of the write cycle.
摘要翻译：半导体存储装置包括：电路，接收基于时钟信号CLK的转变产生读取控制信号（RPB）的指令信号;以及接收用于生成写入控制信号（WPB）的指令信号的电路，时钟信号CLK。基于读取的控制信号来读取单元数据的地址的解码，字线的选择和读出放大器的激活的读取周期以及地址的解码，字线的选择并且基于写控制信号执行写放大器的激活，并且还执行位线预充电，交替执行。读周期的读出周期与写周期的解码周期重叠。

7. 发明申请

US20050181680A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050181680A1
公开(公告)日：2005-08-18
申请号：US11050708
申请日：2005-02-07
申请人： Hiroyuki Takahashi , Masayuki Yanagisawa , Masatoshi Sonoda , Yoshinori Ueno
发明人： Hiroyuki Takahashi , Masayuki Yanagisawa , Masatoshi Sonoda , Yoshinori Ueno
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01R12/00
CPC分类号： H01L23/5258 , H01L21/268 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wherein return wires corresponding to a plurality of fuse wires are arranged collectively in the same region. Moreover, the return wires are arranged in multiple layers. This arrangement creates a region where no return wire is disposed between the fuse wires, thereby permitting an arrangement of the fuse wires at the minimum wiring pitch. Alternatively, the semiconductor device may include fuse strings arranged in a plurality of stages and a plurality of connection wires for supplying signals to the fuse strings in the plurality of stages, respectively, wherein connection wires for other fuse strings are arranged in a region between adjacent fuse strings.
摘要翻译：一种半导体器件，其中对应于多个熔丝的返回线集中地布置在相同的区域中。此外，返回线布置成多层。这种布置形成了在熔丝之间不设置返回布线的区域，从而允许以最小布线间距布置熔丝。或者，半导体器件可以包括分别布置在多个级中的熔丝串和用于分别向多个级中的熔丝串提供信号的多个连接线，其中用于其它熔丝串的连接线布置在相邻保险丝串。

8. 发明授权

US06809989B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US06809989B2
公开(公告)日：2004-10-26
申请号：US10258334
申请日：2002-10-21
申请人： Hiroyuki Takahashi , Masatoshi Sonoda
发明人： Hiroyuki Takahashi , Masatoshi Sonoda
IPC分类号： G11C800
CPC分类号： G11C8/18 , G11C8/06
摘要： A semiconductor memory device is provided which does not malfunction even when noise, generated inside or outside a chip, superimposes on an address. Power source noise is generated internally when a sense amplifier is activated (times t7 and t13) and during data output operations (time t14); in addition, system noise from outside is generated at certain times. By internally capturing an address “Address”, which is input from the outside, at the rise (time t10) of a latch control signal LC, an input sensitivity control signal IC is made valid (times t6-t12) after an address skew period (times t1-t4), and sensitivity with respect to the address is reduced, canceling noise on the address. Furthermore, the latch control signal LC is lowered after a data output operation (time t17). Consequently, this cancellation of the latch state prevents the generation of an incorrect address transition detect signal ATD from the address appearing the noise.

9. 发明申请

US20060271609A1 Semiconductor memory device having matrix of memory banks for multi-bit input/output function 审中-公开
标题翻译：具有用于多位输入/输出功能的存储体矩阵的半导体存储器件
公开(公告)号：US20060271609A1
公开(公告)日：2006-11-30
申请号：US11135465
申请日：2005-05-24
申请人： Hiroyuki Takahashi , Yoshiyuki Katoh , Masatoshi Sonoda
发明人： Hiroyuki Takahashi , Yoshiyuki Katoh , Masatoshi Sonoda
IPC分类号： G06F15/00
CPC分类号： G11C11/4096 , G11C7/1006 , G11C2207/108
摘要： In a semiconductor apparatus for a multi-bit input/output function, a semiconductor memory chip includes 3m rows, 3m columns (m=1, 2, . . . ) of memory banks, each having a plurality of input/output terminals. The memory banks are adapted to carry out the same operation so that a predetermined number of bits are accessed from the input/output terminals of each of the memory banks.
摘要翻译：在用于多位输入/输出功能的半导体装置中，半导体存储器芯片包括3行，3列（m = 1,2，...，），每个存储体具有多个输入/输出端子。存储器组适于执行相同的操作，使得从每个存储体的输入/输出端子访问预定数量的位。

10. 发明授权

US06856566B2 Timer circuit and semiconductor memory incorporating the timer circuit 有权
标题翻译：定时器电路和半导体存储器结合定时器电路
公开(公告)号：US06856566B2
公开(公告)日：2005-02-15
申请号：US10343806
申请日：2001-08-03
申请人： Hiroyuki Takahashi , Masatoshi Sonoda , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Masatoshi Sonoda , Atsushi Nakagawa
IPC分类号： G11C5/00 , G11C7/22 , G11C8/18 , G11C11/406 , G11C11/4074 , G11C11/4076 , H03K3/011 , H03K3/03 , G11C7/00
CPC分类号： H03K3/0315 , G11C7/04 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/406 , G11C11/40626 , G11C11/4074 , G11C11/4076 , H03K3/011
摘要： It is an object to provide a timer circuit which exhibits a tendency of decreasing a timer cycle upon a temperature increase and another tendency of increasing the timer cycle upon a temperature decrease. A diode D has a current characteristic depending upon temperature. A forward current flows through an n-type MOS transistor N1 which forms a primary side of a current mirror. Another current flowing through a p-type MOS transistor P2 and an n-type MOS transistor N3 which form a secondary side of the current mirror is defined depending upon the current flowing through the n-type MOS transistor N1. The current flowing through the p-type MOS transistor P2 and the n-type MOS transistor N3 is supplied as an operating current of a ring oscillator comprising inverters I1˜I3. Accordingly, a cycle (timer cycle) of a clock signal CLK outputted from this ring oscillator reflects a temperature characteristic of the diode D, wherein the timer cycle is decreased with increasing the temperature.
摘要翻译：本发明的目的是提供一种定时器电路，其在温度升高时呈现减小定时器周期的趋势，以及在温度降低时增加定时器周期的另一趋势。二极管D具有取决于温度的电流特性。正向电流流过形成电流镜的初级侧的n型MOS晶体管N1。形成电流镜的二次侧的p型MOS晶体管P2和n型MOS晶体管N3的另一个电流根据流经n型MOS晶体管N1的电流而定义。流过p型MOS晶体管P2和n型MOS晶体管N3的电流作为包括反相器I1〜I3的环形振荡器的工作电流提供。因此，从该环形振荡器输出的时钟信号CLK的周期（定时器周期）反映二极管D的温度特性，其中定时器周期随着温度的升高而降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式