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1. 发明授权

US5619069A Bipolar device and production thereof 失效
标题翻译：双极器件及其生产
公开(公告)号：US5619069A
公开(公告)日：1997-04-08
申请号：US458655
申请日：1995-06-02
申请人： Hiroyuki Ohta , Hideo Miura , Hiroo Masuda , Yoichi Tamaki , Takahide Ikeda , Asao Nishimura , Takashi Hashimoto
发明人： Hiroyuki Ohta , Hideo Miura , Hiroo Masuda , Yoichi Tamaki , Takahide Ikeda , Asao Nishimura , Takashi Hashimoto
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L23/485 , H01L27/06 , H01L29/732 , H01L23/48
CPC分类号： H01L23/4855 , H01L23/485 , H01L2924/0002 , Y10S148/01 , Y10S148/124 , Y10S148/135
摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.
摘要翻译：具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

2. 发明授权

US5643805A Process for producing a bipolar device 失效
标题翻译：用于制造双极器件的方法
公开(公告)号：US5643805A
公开(公告)日：1997-07-01
申请号：US401678
申请日：1995-03-10
申请人： Hiroyuki Ohta , Hideo Miura , Hiroo Masuda , Yoichi Tamaki , Takahide Ikeda , Asao Nishimura , Takashi Hashimoto
发明人： Hiroyuki Ohta , Hideo Miura , Hiroo Masuda , Yoichi Tamaki , Takahide Ikeda , Asao Nishimura , Takashi Hashimoto
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L23/485 , H01L27/06 , H01L29/732 , H01L21/265
CPC分类号： H01L23/4855 , H01L23/485 , H01L2924/0002 , Y10S148/01 , Y10S148/124 , Y10S148/135
摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.
摘要翻译：具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

3. 发明授权

US06337517B1 Semiconductor device and method of fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06337517B1
公开(公告)日：2002-01-08
申请号：US09151590
申请日：1998-09-11
申请人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiroo Masuda
发明人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiroo Masuda
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5
摘要翻译：能够高速运转或具有许多功能的半导体装置。在该装置中，防止了埋入电极的分层，从而提供了高可靠性。接触孔的深度A，下部金属化层的最小线宽R和下部金属化层的厚度B满足关系式

4. 发明授权

US6063686A Method of manufacturing an improved SOI (silicon-on-insulator) semiconductor integrated circuit device 失效
标题翻译：制造改进的SOI（绝缘体上硅）半导体集成电路器件的方法
公开(公告)号：US6063686A
公开(公告)日：2000-05-16
申请号：US23489
申请日：1998-02-13
申请人： Hiroo Masuda , Hisako Sato , Takahide Nakamura , Katsumi Tsuneno , Kimiko Aoyama , Takahide Ikeda , Nobuyoshi Natsuaki , Shinichiro Mitani
发明人： Hiroo Masuda , Hisako Sato , Takahide Nakamura , Katsumi Tsuneno , Kimiko Aoyama , Takahide Ikeda , Nobuyoshi Natsuaki , Shinichiro Mitani
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/339 , H01L21/8242 , H01L21/8247 , H01L21/84 , H01L27/092 , H01L27/108 , H01L27/115 , H01L27/12 , H01L29/762 , H01L29/78 , H01L29/786 , H01L29/788 , H01L29/792 , H01L21/76 , H01L21/30
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78645 , H01L29/78648 , Y10S438/928
摘要： A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer. A gate insulating film for an MISFET is formed over the semiconductor layer; a gate electrode for the MISFET is formed over the gate insulating film, and source and drain region for the MISFET are formed in the semiconductor layer. With this arrangement, the first insulating film serves as a gate insulating film for the MISFET, and the semiconductor film serves as a gate electrode for the MISFET.
摘要翻译：提供一种制造半导体器件的方法，其中制备第一半导体衬底，其具有形成在第一半导体衬底的第一主表面上的第一绝缘膜，形成在第一绝缘膜上的n型导电体的半导体膜，以及第二绝缘膜形成在半导体膜上以覆盖第一主表面。还制备了第二半导体衬底，其具有形成在第二半导体衬底上的第三绝缘膜。接下来，通过热处理将第二绝缘膜和第三绝缘膜接合在一起，以接合第一半导体衬底和第二半导体衬底。然后去除所述第一半导体衬底的与第一半导体衬底的所述第一主表面相对的第二主表面的一部分，以暴露第一半导体衬底的一部分，由此提供半导体层。在半导体层上形成用于MISFET的栅极绝缘膜; 用于MISFET的栅电极形成在栅极绝缘膜上，并且用于MISFET的源极和漏极区域形成在半导体层中。利用这种布置，第一绝缘膜用作MISFET的栅极绝缘膜，并且半导体膜用作MISFET的栅电极。

5. 发明授权

US06949387B2 Method of designing a semiconductor device 失效
标题翻译：设计半导体器件的方法
公开(公告)号：US06949387B2
公开(公告)日：2005-09-27
申请号：US10626718
申请日：2003-07-25
申请人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L21/66
CPC分类号： H01L21/76205 , H01L21/76202 , H01L27/0802
摘要： A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.
摘要翻译：提供了一种半导体器件的技术，其包括在器件形成区域上形成电路区域和半导体衬底上的器件隔离区域，器件隔离区域的宽度与其相邻电路区域的宽度的比率被设置为2至还提供了一种设计方法，包括进行测量，例如衬垫氧化膜和氮化物膜的厚度，氮化物膜的内部应力，器件形成和隔离区域的宽度，蚀刻部分的深度的用于在器件隔离区域中形成沟槽的氮化物膜，由于热氧化而在沟槽附近进行导电应力分析，以及与器件形成区域的宽度和不引导的器件隔离区域的设定值发生脱位。

6. 发明授权

US5889312A Semiconductor device having circuit element in stress gradient region by film for isolation and method of manufacturing the same 失效
标题翻译：具有用于隔离膜的应力梯度区域中的电路元件的半导体器件及其制造方法
公开(公告)号：US5889312A
公开(公告)日：1999-03-30
申请号：US890997
申请日：1997-07-10
申请人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L3/22 , H01L21/265
CPC分类号： H01L21/76202 , H01L27/0802
摘要： A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.
摘要翻译：半导体器件包括用于隔离的热氧化膜，半导体区域，其成为元件形成区域，其周边被半导体区域中的氧化物膜和扩散电阻层包围，并且提供用于控制起始的扩散电阻器的电阻值变化的结构在形成用于隔离的氧化膜时产生的应力。最靠近扩散层的热氧化膜的较长侧的端部与热氧化膜的端部之间的距离彼此分开由半导体区域中的应力分布确定的预定值或至少4 从热氧化膜的端部到半导体区域的应力分布（梯度）形成区域形成的扩散层部的纵向方向平行于应力梯度的形成方向，电阻值分布形成为平行于从热氧化膜的端部到半导体区域中的应力分布形成区域形成的扩散层中的应力梯度。

7. 发明授权

US06310384B1 Low stress semiconductor devices with thermal oxide isolation 失效
标题翻译：具有热氧化隔离的低应力半导体器件
公开(公告)号：US06310384B1
公开(公告)日：2001-10-30
申请号：US08838259
申请日：1997-04-17
申请人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L2900
CPC分类号： H01L21/76205 , H01L21/76202 , H01L27/0802
摘要： A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. In accordance with the manufacturing scheme, a semiconductor device produced includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.01 to 2.5 &mgr;m. In such a schemed device, a ratio of the width of the device region to the width of the device isolation region is from 2 to 50. Each device isolation region is a groove formed in the semiconductor substrate by etching a portion, among the pad oxide film formed on the surface of the semiconductor substrate and a nitride film formed on the pad oxide film, existing on the device isolation region, and having a depth of from 0 to 10 nm when measured from the position of the pad oxide film on the semiconductor substrate.
摘要翻译：确定电路器件隔离区域的宽度和形成在半导体衬底上的器件区域的宽度，以满足防止由于形成隔离区域的热氧化引起的位错发生的条件。根据制造方案，制造的半导体器件包括半导体衬底，形成在半导体衬底中的器件形成区域上并具有0.1至125μm的宽度的多个电路区域和形成在半导体衬底上的器件隔离区域以便将多个电路区彼此隔离并且具有0.01至2.5μm的宽度。在这种设计的器件中，器件区域的宽度与器件隔离区域的宽度的比率为2至50.每个器件隔离区域是通过在衬底氧化物中蚀刻一部分而形成在半导体衬底中的沟槽形成在半导体衬底的表面上的膜和形成在衬垫氧化膜上的氮化物膜，存在于器件隔离区上，并且当从半导体上的衬垫氧化物膜的位置测量时具有0至10nm的深度基质。

8. 发明授权

US06620704B2 Method of fabricating low stress semiconductor devices with thermal oxide isolation 失效
标题翻译：制造具有热氧化隔离的低应力半导体器件的方法
公开(公告)号：US06620704B2
公开(公告)日：2003-09-16
申请号：US09893980
申请日：2001-06-29
申请人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L2176
CPC分类号： H01L21/76205 , H01L21/76202 , H01L27/0802
摘要： A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括在半导体衬底上形成氧化硅膜。可以在氧化硅膜上形成亚硝酸硅膜。可以在期望的部分去除一部分亚硝酸硅膜和氧化硅膜。此外，可以在除去氧化硅膜的部分中的半导体衬底中形成沟槽。氧化硅膜的一部分可以在硅亚硝酸盐膜位于上方的部分用氢氟酸型蚀刻回到槽周围。此外，可以在半导体衬底的沟槽中形成氧化膜，并且可以使沟槽被氧化。

9. 发明授权

US5119332A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5119332A
公开(公告)日：1992-06-02
申请号：US515345
申请日：1990-04-30
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Hiroshi Kawamoto
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Hiroshi Kawamoto
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108
CPC分类号： H01L27/108 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/10805 , H01L2924/0002 , H01L2924/3011
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed to a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.
摘要翻译：单元存储单元型的动态RAM集成电路设置有多条数据线，读出放大器，以与数据线相交的方式设置的多条字线，以及设置在数据线上的存储单元数据线与字线之间的交点。 RAM包括P型半导体衬底和形成在衬底中的N型阱区。存储单元设置在阱内，并且连接到日期线的读出放大器被构造成形成在半导体衬底中的一对N沟道MOSFET和形成在阱区中的一对P沟道MOSFET 。

10. 发明授权

US4539658A Semiconductor memory 失效
公开(公告)号：US4539658A
公开(公告)日：1985-09-03
申请号：US638982
申请日：1984-08-08
申请人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
发明人： Katsuhiro Shimohigashi , Hiroo Masuda , Kunihiko Ikuzaki , Hiroshi Kawamoto
IPC分类号： G11C11/419 , G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/04 , H01L27/092 , H01L27/10 , H01L27/108 , G11C11/40 , H01L29/78
CPC分类号： G11C11/409 , G11C11/4091 , G11C11/4096 , G11C11/4097 , H01L23/522 , H01L27/108 , H01L27/10805 , H01L2924/0002 , H01L2924/3011 , Y10S148/164
摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

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