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1. 发明申请

US20060044008A1 Resistance compensation method, circuit having a resistance compensation function, and circuit resistance test method 有权
标题翻译：电阻补偿方法，具有电阻补偿功能的电路和电路电阻测试方法
公开(公告)号：US20060044008A1
公开(公告)日：2006-03-02
申请号：US11017880
申请日：2004-12-22
申请人： Hiroshi Miyake , Noriyuki Tokuhiro , Tadao Aikawa , Hiroshi Miyazaki
发明人： Hiroshi Miyake , Noriyuki Tokuhiro , Tadao Aikawa , Hiroshi Miyazaki
IPC分类号： H03K19/003
CPC分类号： H04L25/0298 , G11C7/1048 , G11C2207/2254 , H03K17/164
摘要： A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.
摘要翻译：公开了一种用于补偿半导体器件电阻的方法，其包括通过多个半导体器件的组合之一实现等于期望电阻的电阻的步骤。该步骤包括顺序地选择要组合的半导体器件中的两个或更多个的步骤，从而顺序地改变由所选择的两个或更多个要组合的半导体器件实现的电阻。

2. 发明授权

US07193431B2 Resistance compensation method, circuit having a resistance compensation function, and circuit resistance test method 有权
标题翻译：电阻补偿方法，具有电阻补偿功能的电路和电路电阻测试方法
公开(公告)号：US07193431B2
公开(公告)日：2007-03-20
申请号：US11017880
申请日：2004-12-22
申请人： Hiroshi Miyake , Noriyuki Tokuhiro , Tadao Aikawa , Hiroshi Miyazaki
发明人： Hiroshi Miyake , Noriyuki Tokuhiro , Tadao Aikawa , Hiroshi Miyazaki
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0298 , G11C7/1048 , G11C2207/2254 , H03K17/164
摘要： A method for compensating for semiconductor device resistance is disclosed that includes the step of realizing a resistance equal to a desired resistance by one of combinations of multiple semiconductor devices. This step includes the step of sequentially selecting two or more of the semiconductor devices to be combined, and thereby sequentially changing a resistance realized by the selected two or more of the semiconductor devices to be combined.
摘要翻译：公开了一种用于补偿半导体器件电阻的方法，其包括通过多个半导体器件的组合之一实现等于期望电阻的电阻的步骤。该步骤包括顺序地选择要组合的半导体器件中的两个或更多个的步骤，从而顺序地改变由所选择的两个或更多个要组合的半导体器件实现的电阻。

3. 发明申请

US20060043999A1 Semiconductor circuit, method of monitoring semiconductor-circuit performance, method of testing semiconductor circuit, equipment for testing semiconductor circuit, and program for testing semiconductor circuit 有权
标题翻译：半导体电路，半导体电路性能监控方法，半导体电路测试方法，半导体电路测试设备以及半导体电路测试程序
公开(公告)号：US20060043999A1
公开(公告)日：2006-03-02
申请号：US11019238
申请日：2004-12-23
申请人： Hiroshi Miyake , Noriyuki Tokuhiro
发明人： Hiroshi Miyake , Noriyuki Tokuhiro
IPC分类号： G01R31/26
CPC分类号： H03L7/0814
摘要： A semiconductor circuit is disclosed, including a DLL circuit for supplying a desired signal-delay amount. The DLL circuit includes detecting means for detecting variations of a signal-delay amount, and delay-amount control means for generating a delay-amount control signal for controlling, depending on the variations of the signal-delay amount detected by the detecting means, the signal-delay amount of the DLL circuit. The semiconductor circuit further includes a part for monitoring circuit performance of the semiconductor circuit based on the delay-amount control signal.
摘要翻译：公开了一种半导体电路，包括用于提供期望的信号延迟量的DLL电路。 DLL电路包括用于检测信号延迟量的变化的检测装置，以及延迟量控制装置，用于根据由检测装置检测的信号延迟量的变化产生用于控制的延迟量控制信号， DLL电路的信号延迟量。半导体电路还包括用于基于延迟量控制信号监视半导体电路的电路性能的部分。

4. 发明授权

US07274200B2 Semiconductor circuit, method of monitoring semiconductor-circuit performance, method of testing semiconductor circuit, equipment for testing semiconductor circuit, and program for testing semiconductor circuit 有权
标题翻译：半导体电路，半导体电路性能监控方法，半导体电路测试方法，半导体电路测试设备以及半导体电路测试程序
公开(公告)号：US07274200B2
公开(公告)日：2007-09-25
申请号：US11019238
申请日：2004-12-23
申请人： Hiroshi Miyake , Noriyuki Tokuhiro
发明人： Hiroshi Miyake , Noriyuki Tokuhiro
IPC分类号： G01R31/02
CPC分类号： H03L7/0814
摘要： A semiconductor circuit is disclosed, including a DLL circuit for supplying a desired signal-delay amount. The DLL circuit includes detecting means for detecting variations of a signal-delay amount, and delay-amount control means for generating a delay-amount control signal for controlling, depending on the variations of the signal-delay amount detected by the detecting means, the signal-delay amount of the DLL circuit. The semiconductor circuit further includes a part for monitoring circuit performance of the semiconductor circuit based on the delay-amount control signal.
摘要翻译：公开了一种半导体电路，包括用于提供期望的信号延迟量的DLL电路。 DLL电路包括用于检测信号延迟量的变化的检测装置，以及延迟量控制装置，用于根据由检测装置检测的信号延迟量的变化产生用于控制的延迟量控制信号， DLL电路的信号延迟量。半导体电路还包括用于基于延迟量控制信号监视半导体电路的电路性能的部分。

5. 发明授权

US08788780B2 Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method 有权
标题翻译：信号恢复电路，延迟调整电路，存储器控制器，处理器，计算机，信号恢复方法和延迟调整方法
公开(公告)号：US08788780B2
公开(公告)日：2014-07-22
申请号：US13472575
申请日：2012-05-16
申请人： Noriyuki Tokuhiro , Noriyuki Takahashi , Shinya Aiso
发明人： Noriyuki Tokuhiro , Noriyuki Takahashi , Shinya Aiso
IPC分类号： G06F12/00 , G11C11/4076 , G11C7/22
CPC分类号： G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.
摘要翻译：信号恢复电路包括：存储器，被配置为通过以输入顺序布置输入信号来存储输入信号，所述输入信号以所述排列顺序从所述存储器读取;以及存储控制器，被配置为控制来自所述输入的输入的延迟时间基于输入信号的延迟信息向存储器中的输出发送信号。

6. 发明授权

US07298192B2 Digital DLL device, digital DLL control method, and digital DLL control program 失效
标题翻译：数字DLL设备，数字DLL控制方法和数字DLL控制程序
公开(公告)号：US07298192B2
公开(公告)日：2007-11-20
申请号：US11510721
申请日：2006-08-28
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.
摘要翻译：提供一种数字DLL设备，其可以减少相对于目标延迟量的错误。该装置向输入时钟信号提供延迟，以便将其时钟周期T均等地划分为N个部分，并且包括第一可变延迟部分和第二可变延迟部分，每个可变延迟部分和第二可变延迟部分由连接的任意数量的单位延迟缓冲器相互串联。相位比较部分比较输入时钟信号的相位和输入信号的相位，该输出信号是通过所有第一和第二可变延迟部分时被延迟的输入信号，并输出比较结果。延迟控制部分根据相位比较结果计算所需的单位延迟缓冲器S的总数，将S除以N的商Q设定为每个第一可变延迟部分的单位延迟缓冲器的数量，并且分配 S的余数R除以N分别与第二可变延迟部分。

7. 发明授权

US07154981B2 Termination circuit 有权
标题翻译：终端电路
公开(公告)号：US07154981B2
公开(公告)日：2006-12-26
申请号：US10982778
申请日：2004-11-08
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0298
摘要： A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.
摘要翻译：用于终止传输线的终端电路包括通过并联连接P沟道型MOS晶体管和N沟道型MOS晶体管而形成的电阻单元，并且通过在传输线和电源线和传输线与接地线之间。

8. 发明申请

US20120153988A1 SEMICONDUCTOR DEVICE, CIRCUIT BOARD DEVICE, AND INFORMATION PROCESSING DEVICE 有权
标题翻译：半导体器件，电路板器件和信息处理器件
公开(公告)号：US20120153988A1
公开(公告)日：2012-06-21
申请号：US13239877
申请日：2011-09-22
申请人： Noriyuki Tokuhiro , Kazumasa Kubotera , Yasutaka Kanayama
发明人： Noriyuki Tokuhiro , Kazumasa Kubotera , Yasutaka Kanayama
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , G06F2213/0038 , H03K19/018571 , H03K19/018585 , H04L25/0278
摘要： In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.
摘要翻译：在半导体器件中，选择器根据发送器或接收器的阻抗是否调整而选择不同的参考电压，并且使参考电压发生器产生所选择的参考电压。参考电压发生器产生由选择器选择的参考电压，并将产生的参考电压施加到阻抗调节器。阻抗调节器根据输入参考电压分别调整发射器的阻抗和接收器的阻抗。

9. 发明授权

US08020022B2 Delay time control of memory controller 失效
标题翻译：内存控制器的延迟时间控制
公开(公告)号：US08020022B2
公开(公告)日：2011-09-13
申请号：US12209740
申请日：2008-09-12
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： G06F13/42
CPC分类号： G11C7/1078 , G06F13/1689 , G11C7/10 , G11C7/1093
摘要： A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the plurality of memories, a first variable delay unit delays, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function and a second variable delay unit delays, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time.
摘要翻译：存储器控制电路具有写调平功能，并且通过通过菊花链连接连接到多个存储器的时钟信号线向多个存储器提供时钟信号来控制读/写操作。对于多个存储器中的每一个，第一可变延迟单元在写入操作中将通过利用写入调平功能设置的第一延迟时间和第二可变延迟单元延迟输出到存储器的数据选通信号延迟，在读取操作中，从存储器输入基于第一延迟时间设置的第二延迟时间的数据信号。

10. 发明授权

US07102553B2 Signal transmission method and signal transmission device 失效
公开(公告)号：US07102553B2
公开(公告)日：2006-09-05
申请号：US11202351
申请日：2005-08-10
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： H03M9/00
CPC分类号： H04L25/45 , H03M9/00 , H04L25/4908
摘要： A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+α with bit count N is longitudinal-lateral converted into a data signal of time slot count N with bit count N+α. so as to create a null time α and a control signal is inserted into the null time α, thereby converting the parallel signal containing the data signal and the control signal into a serial signal for transmission.

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