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1. 发明授权

US08788780B2 Signal restoration circuit, latency adjustment circuit, memory controller, processor, computer, signal restoration method, and latency adjustment method 有权
标题翻译：信号恢复电路，延迟调整电路，存储器控制器，处理器，计算机，信号恢复方法和延迟调整方法
公开(公告)号：US08788780B2
公开(公告)日：2014-07-22
申请号：US13472575
申请日：2012-05-16
申请人： Noriyuki Tokuhiro , Noriyuki Takahashi , Shinya Aiso
发明人： Noriyuki Tokuhiro , Noriyuki Takahashi , Shinya Aiso
IPC分类号： G06F12/00 , G11C11/4076 , G11C7/22
CPC分类号： G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.
摘要翻译：信号恢复电路包括：存储器，被配置为通过以输入顺序布置输入信号来存储输入信号，所述输入信号以所述排列顺序从所述存储器读取;以及存储控制器，被配置为控制来自所述输入的输入的延迟时间基于输入信号的延迟信息向存储器中的输出发送信号。

2. 发明申请

US20120242385A1 SIGNAL RECEIVING CIRCUIT, MEMORY CONTROLLER, PROCESSOR, COMPUTER, AND PHASE CONTROL METHOD 有权
标题翻译：信号接收电路，存储器控制器，处理器，计算机和相位控制方法
公开(公告)号：US20120242385A1
公开(公告)日：2012-09-27
申请号：US13493421
申请日：2012-06-11
申请人： Noriyuki TOKUHIRO
发明人： Noriyuki TOKUHIRO
IPC分类号： H03L7/06
CPC分类号： G11C7/1066 , G06F13/1689 , H04L7/0008 , H04L7/0033 , H04L7/0037
摘要： A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.
摘要翻译：信号接收电路包括相位检测单元和延迟控制单元。相位检测单元检测接收信号和时钟信号之间的相位差。延迟控制单元接收相位差，在不超过以预定相位差确定的延迟量的范围内将接收信号的相位延迟为一个单位，并且当相位差超过预定相位差时改变延迟通过使用预定的相位差作为一个单位的接收信号量。

3. 发明授权

US07298192B2 Digital DLL device, digital DLL control method, and digital DLL control program 失效
标题翻译：数字DLL设备，数字DLL控制方法和数字DLL控制程序
公开(公告)号：US07298192B2
公开(公告)日：2007-11-20
申请号：US11510721
申请日：2006-08-28
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： H03L7/06
CPC分类号： H03L7/0814
摘要： A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.
摘要翻译：提供一种数字DLL设备，其可以减少相对于目标延迟量的错误。该装置向输入时钟信号提供延迟，以便将其时钟周期T均等地划分为N个部分，并且包括第一可变延迟部分和第二可变延迟部分，每个可变延迟部分和第二可变延迟部分由连接的任意数量的单位延迟缓冲器相互串联。相位比较部分比较输入时钟信号的相位和输入信号的相位，该输出信号是通过所有第一和第二可变延迟部分时被延迟的输入信号，并输出比较结果。延迟控制部分根据相位比较结果计算所需的单位延迟缓冲器S的总数，将S除以N的商Q设定为每个第一可变延迟部分的单位延迟缓冲器的数量，并且分配 S的余数R除以N分别与第二可变延迟部分。

4. 发明授权

US07154981B2 Termination circuit 有权
标题翻译：终端电路
公开(公告)号：US07154981B2
公开(公告)日：2006-12-26
申请号：US10982778
申请日：2004-11-08
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0298
摘要： A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.
摘要翻译：用于终止传输线的终端电路包括通过并联连接P沟道型MOS晶体管和N沟道型MOS晶体管而形成的电阻单元，并且通过在传输线和电源线和传输线与接地线之间。

5. 发明授权

US08723569B2 Signal receiving circuit, memory controller, processor, computer, and phase control method 有权
标题翻译：信号接收电路，存储器控制器，处理器，计算机和相位控制方法
公开(公告)号：US08723569B2
公开(公告)日：2014-05-13
申请号：US13493421
申请日：2012-06-11
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： H03L7/06
CPC分类号： G11C7/1066 , G06F13/1689 , H04L7/0008 , H04L7/0033 , H04L7/0037
摘要： A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.
摘要翻译：信号接收电路包括相位检测单元和延迟控制单元。相位检测单元检测接收信号和时钟信号之间的相位差。延迟控制单元接收相位差，在不超过以预定相位差确定的延迟量的范围内将接收信号的相位延迟为一个单位，并且当相位差超过预定相位差时改变延迟通过使用预定相位差作为一个单位的接收信号量。

6. 发明申请

US20060022713A1 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US20060022713A1
公开(公告)日：2006-02-02
申请号：US10986154
申请日：2004-11-12
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K19/094
CPC分类号： H03K19/0005 , H03K19/018585
摘要： A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power base of two with the same polarity belong and in which the number of driving transistors belonging to each group is different and a driving unit for driving driving transistors belonging to the group selected by the selection unit.
摘要翻译：一种用于驱动设置在其上的器件或电路的驱动器电路，其包括并联连接的多个驱动晶体管，用于从多个组中选择一个或多个组的选择单元，其中驱动晶体管的功率基数为2，属于每个组的驱动晶体管的数量不同的驱动单元和属于由选择单元选择的组的驱动晶体管的驱动单元相同。

7. 发明申请

US20060022702A1 Interface circuit and constituting method thereof 审中-公开
标题翻译：接口电路及其构成方法
公开(公告)号：US20060022702A1
公开(公告)日：2006-02-02
申请号：US10989461
申请日：2004-11-17
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K19/003
CPC分类号： H03K19/018592 , H03K19/018585 , H04L25/0278
摘要： An interface circuit which is connected to a function unit such as a memory reduces the number of structural elements by using structural elements in common, and also realizes a plurality of different function circuits. The interface circuit connected with the function unit uses the structural elements for a plurality of circuits in common, and obtains necessary functions by controlling the structural elements. The interface circuit has first and second electronic devices such as FETs connected in series, and an external terminal, formed at an intermediate connected portion between the first electronic device and the second electronic device, to which the function unit is connected, and constitutes a function circuit part having different functions by controlling the first electronic device and the second electronic device.
摘要翻译：连接到诸如存储器的功能单元的接口电路通过共同使用结构元件来减少结构元件的数量，并且还实现多个不同的功能电路。与功能单元连接的接口电路共同地使用多个电路的结构元件，并且通过控制结构元件来获得必要的功能。接口电路具有串联连接的诸如FET的第一和第二电子器件，以及形成在第一电子器件与第二电子器件之间的中间连接部分处的功能单元连接的外部端子，并且构成功能电路部件通过控制第一电子设备和第二电子设备而具有不同的功能。

8. 发明申请

US20060012497A1 Signal transmission method and signal transmission device 失效
标题翻译：信号传输方式及信号传输装置
公开(公告)号：US20060012497A1
公开(公告)日：2006-01-19
申请号：US11202351
申请日：2005-08-10
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： H03M9/00
CPC分类号： H04L25/45 , H03M9/00 , H04L25/4908
摘要： A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+α with bit count N is longitudinal-lateral converted into a data signal of time slot count N with bit count N+α. so as to create a null time α and a control signal is inserted into the null time α, thereby converting the parallel signal containing the data signal and the control signal into a serial signal for transmission.
摘要翻译：一种能够容易地发送具有少量信号线的信号的信号传输方法和信号传输装置。具有位计数N的时隙计数N +α的数据信号被纵向 - 横向转换成具有位计数N +α的时隙计数N的数据信号。以创建空时alpha，并且将控制信号插入到空时间α，从而将包含数据信号和控制信号的并行信号转换为串行信号以进行传输。

9. 发明授权

US06275073B1 Differential input circuit 失效
标题翻译：差分输入电路
公开(公告)号：US06275073B1
公开(公告)日：2001-08-14
申请号：US09401304
申请日：1999-09-23
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： H03K522
CPC分类号： H04L25/0294 , H03K5/2481 , H04L25/0272
摘要： A differential input circuit which can positively operate over a wide input range is provided. The differential input circuit includes a first constant current source of a current mirror type which generates a positive current and a second constant current source of a current mirror type which generates a negative current. The first and second constant current sources constitute a differential amplifier circuit. A current switch which is connected to a positive input and a negative input is also connected to said first and second constant current sources so that an operating point of the differential amplifier circuit can be changed.
摘要翻译：提供了可以在宽输入范围内正向工作的差分输入电路。差分输入电路包括产生正电流的电流镜型的第一恒定电流源和产生负电流的电流镜型的第二恒流源。第一和第二恒流源构成差分放大器电路。连接到正输入和负输入的电流开关也连接到所述第一和第二恒流源，使得可以改变差分放大器电路的工作点。

10. 发明授权

US5307065A Digital-to-analog converter 失效
标题翻译：数模转换器
公开(公告)号：US5307065A
公开(公告)日：1994-04-26
申请号：US674332
申请日：1991-04-19
申请人： Noriyuki Tokuhiro
发明人： Noriyuki Tokuhiro
IPC分类号： H03M1/74 , H03M1/70 , H03M1/80 , H03M1/66
CPC分类号： H03M1/70 , H03M1/808
摘要： A digital-to-analog converter of a current addition type using weighted resistors, includes an input resistor network (4) for providing a resistance dependent on a digital input signal having a predetermined number of bits, and an adder (3) having a first input terminal coupled to the input resistor network and a second input terminal connectable to receive a reference potential, for adding a signal obtained at the first input terminal and the reference potential. The adder also has an output terminal via which a result of an adding operation is output, and the result of the adding operation shows an analog signal corresponding to the digital input signal. The digital-to-analog converter also includes a feedback resistor network (5) provided between the first input terminal and the output terminal of the adder, the feedback resistor network providing a feedback resistance dependent on a control signal indicating a magnitude of the digital input signal, and a feedback resistor network control circuit (7) for generating the control signal indicating the magnitude of the digital input signal from the digital input signal.
摘要翻译： PCT No.PCT / JP90 / 01055 Sec。 371日期1991年04月19日 102（e）日期1991年4月19日PCT提交1990年8月20日PCT公布。公开号WO91 / 03105 日期：1991年3月7日。一种使用加权电阻的电流相加型数模转换器，包括一个输入电阻网络（4），用于提供取决于具有预定位数的数字输入信号的电阻，以及加法器（3）具有耦合到输入电阻网络的第一输入端和可连接以接收参考电位的第二输入端，用于将在第一输入端获得的信号和参考电位相加。加法器还具有输出端子，通过该输出端子输出相加运算的结果，加法运算结果显示与数字输入信号对应的模拟信号。数模转换器还包括设置在加法器的第一输入端和输出端之间的反馈电阻网络（5），反馈电阻网络根据指示数字输入幅度的控制信号提供反馈电阻信号和反馈电阻网络控制电路（7），用于从数字输入信号产生指示数字输入信号幅度的控制信号。

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