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1. 发明授权

US07053660B2 Output buffer circuit and control method therefor 有权
标题翻译：输出缓冲电路及其控制方法
公开(公告)号：US07053660B2
公开(公告)日：2006-05-30
申请号：US11121130
申请日：2005-05-04
申请人： Kunihiro Itoh , Osamu Uno
发明人： Kunihiro Itoh , Osamu Uno
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/00361 , H03K17/167
摘要： An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.
摘要翻译：输出缓冲器包括接收具有尖锐波形的输入信号的第一驱动电路，并产生具有平缓波形的输出信号。第二驱动电路在输出端子处连接到第一驱动电路，并且具有比第一驱动电路低的阻抗。延迟电路也连接到输出端子并产生延迟的输出信号。第一控制电路连接在延迟电路和第二驱动电路之间，并接收输入信号和延迟的输出信号，并产生用于驱动第二驱动电路的第一控制信号。

2. 发明授权

US07088167B2 Level conversion for use in semiconductor device 有权
标题翻译：用于半导体器件的电平转换
公开(公告)号：US07088167B2
公开(公告)日：2006-08-08
申请号：US11044030
申请日：2005-01-28
申请人： Kunihiro Itoh
发明人： Kunihiro Itoh
IPC分类号： H03L5/00
CPC分类号： H03K3/356017 , H03K17/102
摘要： In an operation to supply an input signal IN having an amplitude equal to a first power-supply voltage VDD1 to the gate of a PMOS transistor PM51 operating at a second power-supply voltage VDD2 higher than the first power-supply voltage VDD1, the levels of signals are converted by using PMOS transistors PM1 to PM4. A signal obtained as a result of the conversion is output from the PMOS transistors PM1 and PM2, being used for controlling electrical conduction of a PMOS transistor PM51.
摘要翻译：在将第一电源电压VDD 1的幅度等于第一电源电压VDD1的输入信号IN的电源供给到高于第一电源电压VDD的第二电源电压VDD2的PMOS晶体管PM51的栅极的操作中如图1所示，通过使用PMOS晶体管PM 1〜PM 4来转换信号电平。作为转换结果而获得的信号从用于控制PMOS晶体管PM 51的导通的PMOS晶体管PM 1和PM 2输出。

3. 发明申请

US20060022713A1 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US20060022713A1
公开(公告)日：2006-02-02
申请号：US10986154
申请日：2004-11-12
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K19/094
CPC分类号： H03K19/0005 , H03K19/018585
摘要： A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power base of two with the same polarity belong and in which the number of driving transistors belonging to each group is different and a driving unit for driving driving transistors belonging to the group selected by the selection unit.
摘要翻译：一种用于驱动设置在其上的器件或电路的驱动器电路，其包括并联连接的多个驱动晶体管，用于从多个组中选择一个或多个组的选择单元，其中驱动晶体管的功率基数为2，属于每个组的驱动晶体管的数量不同的驱动单元和属于由选择单元选择的组的驱动晶体管的驱动单元相同。

4. 发明申请

US20060022702A1 Interface circuit and constituting method thereof 审中-公开
标题翻译：接口电路及其构成方法
公开(公告)号：US20060022702A1
公开(公告)日：2006-02-02
申请号：US10989461
申请日：2004-11-17
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K19/003
CPC分类号： H03K19/018592 , H03K19/018585 , H04L25/0278
摘要： An interface circuit which is connected to a function unit such as a memory reduces the number of structural elements by using structural elements in common, and also realizes a plurality of different function circuits. The interface circuit connected with the function unit uses the structural elements for a plurality of circuits in common, and obtains necessary functions by controlling the structural elements. The interface circuit has first and second electronic devices such as FETs connected in series, and an external terminal, formed at an intermediate connected portion between the first electronic device and the second electronic device, to which the function unit is connected, and constitutes a function circuit part having different functions by controlling the first electronic device and the second electronic device.
摘要翻译：连接到诸如存储器的功能单元的接口电路通过共同使用结构元件来减少结构元件的数量，并且还实现多个不同的功能电路。与功能单元连接的接口电路共同地使用多个电路的结构元件，并且通过控制结构元件来获得必要的功能。接口电路具有串联连接的诸如FET的第一和第二电子器件，以及形成在第一电子器件与第二电子器件之间的中间连接部分处的功能单元连接的外部端子，并且构成功能电路部件通过控制第一电子设备和第二电子设备而具有不同的功能。

5. 发明授权

US4586027A Method and system for data compression and restoration 失效
标题翻译：用于数据压缩和恢复的方法和系统
公开(公告)号：US4586027A
公开(公告)日：1986-04-29
申请号：US638424
申请日：1984-08-07
申请人： Tokuhiro Tsukiyama , Yoshie Kondo , Katsuharu Kakuse , Shinpei Saba , Syoji Ozaki , Kunihiro Itoh
发明人： Tokuhiro Tsukiyama , Yoshie Kondo , Katsuharu Kakuse , Shinpei Saba , Syoji Ozaki , Kunihiro Itoh
IPC分类号： G06F3/06 , G11B20/00 , G11B20/10 , G11B20/12 , H03M7/48 , G06F5/00
CPC分类号： H03M7/48 , G11B20/00007
摘要： Method of data compression and restoration wherein an input data string including repetitive data more in number than the specified value is transformed into a data string having a format including the first region where non-compressed data are placed, the second region including a datum representative of a data string section which has undergone the compression process and information indicative of the number of repetitive data, i.e., the length of the data string section, and control information inserted at the front and back of the first region indicative of the number of data included in the first region, said transformed data string being recorded on the recording medium, and, for data reproduction, the first and second regions are identified on the basis of the control information read out on the recording medium so that the compressed data string section is transformed back to the original data string in the form of repetitive data.
摘要翻译：数据压缩和恢复方法，其中包括数量大于指定值的重复数据的输入数据串被转换成具有格式的数据串，该格式包括放置非压缩数据的第一区域，第二区域包括代表经历了压缩处理的数据串部分和指示重复数据的数量的信息，即数据串部分的长度，以及插入在第一区域的前后的控制信息，指示包括的数据的数量在第一区域中，所述变换数据串被记录在记录介质上，并且为了数据再现，基于在记录介质上读出的控制信息来识别第一和第二区域，使得压缩数据串段是以重复数据的形式转换回原始数据串。

6. 发明授权

US07154981B2 Termination circuit 有权
标题翻译：终端电路
公开(公告)号：US07154981B2
公开(公告)日：2006-12-26
申请号：US10982778
申请日：2004-11-08
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0298
摘要： A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.
摘要翻译：用于终止传输线的终端电路包括通过并联连接P沟道型MOS晶体管和N沟道型MOS晶体管而形成的电阻单元，并且通过在传输线和电源线和传输线与接地线之间。

7. 发明授权

US06924669B2 Output buffer circuit and control method therefor 有权
标题翻译：输出缓冲电路及其控制方法
公开(公告)号：US06924669B2
公开(公告)日：2005-08-02
申请号：US09735555
申请日：2000-12-14
申请人： Kunihiro Itoh , Osamu Uno
发明人： Kunihiro Itoh , Osamu Uno
IPC分类号： H03K19/0185 , H03K17/16 , H03K19/003 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/00361 , H03K17/167
摘要： An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.
摘要翻译：输出缓冲器包括接收具有尖锐波形的输入信号的第一驱动电路，并产生具有平缓波形的输出信号。第二驱动电路在输出端子处连接到第一驱动电路，并且具有比第一驱动电路低的阻抗。延迟电路也连接到输出端子并产生延迟的输出信号。第一控制电路连接在延迟电路和第二驱动电路之间，并接收输入信号和延迟的输出信号，并产生用于驱动第二驱动电路的第一控制信号。

8. 发明申请

US20050127977A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050127977A1
公开(公告)日：2005-06-16
申请号：US11044030
申请日：2005-01-28
申请人： Kunihiro Itoh
发明人： Kunihiro Itoh
IPC分类号： H03K3/356 , H03K17/10 , H03K19/0185 , H03L7/00
CPC分类号： H03K3/356017 , H03K17/102
摘要： In an operation to supply an input signal IN having an amplitude equal to a first power-supply voltage VDD1 to the gate of a PMOS transistor PM51 operating at a second power-supply voltage VDD2 higher than the first power-supply voltage VDD1, the levels of signals are converted by using PMOS transistors PM1 to PM4. The sources of the PMOS transistors PM1 and PM3 are connected to a line of the first power-supply voltage VDD1 whereas the sources of the PMOS transistors PM2 and PM4 are connected to a line of the second power-supply voltage VDD2. The gate of the PMOS transistor PM4 is connected to the drains of the PMOS transistors PM1 and PM2. The gate of the PMOS transistor PM2 is connected to the drains of the PMOS transistors PM3 and PM4. An inverted signal of the input signal IN is supplied to the gate of the PMOS transistor PM1 and the input signal IN is supplied to the gate of the PMOS transistor PM2. The amplitude of the input signal IN is converted from a magnitude equal to a difference between a reference signal VSS and the first power-supply voltage VDD1 into a magnitude equal to a difference between the first power-supply voltage VDD1 and the second power-supply voltage VDD2. A signal obtained as a result of the conversion is output from the PMOS transistors PM1 and PM2, being used for controlling electrical conduction of a PMOS transistor PM51.
摘要翻译：在将第一电源电压VDD 1的幅度等于第一电源电压VDD1的输入信号IN的电源供给到高于第一电源电压VDD的第二电源电压VDD2的PMOS晶体管PM51的栅极的操作中如图1所示，通过使用PMOS晶体管PM 1〜PM 4来转换信号电平。 PMOS晶体管PM 1和PM 3的源极连接到第一电源电压VDD1的一行，而PMOS晶体管PM 2和PM 4的源极连接到第二电源电压VDD的一行 2。 PMOS晶体管PM4的栅极连接到PMOS晶体管PM 1和PM 2的漏极。 PMOS晶体管PM2的栅极连接到PMOS晶体管PM 3和PM 4的漏极。输入信号IN的反相信号被提供给PMOS晶体管PM1的栅极，并且输入信号IN被提供给PMOS晶体管PM2的栅极。将输入信号IN的振幅从等于参考信号VSS和第一电源电压VDD 1之间的差的幅度转换成等于第一电源电压VDD 1和第二电源之间的差的幅度供电电压VDD 2。作为转换结果而获得的信号从用于控制PMOS晶体管PM 51的导通的PMOS晶体管PM 1和PM 2输出。

9. 发明授权

US07362127B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US07362127B2
公开(公告)日：2008-04-22
申请号：US10986154
申请日：2004-11-12
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , H03K19/018585
摘要： A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power base of two with the same polarity belong and in which the number of driving transistors belonging to each group is different and a driving unit for driving driving transistors belonging to the group selected by the selection unit.
摘要翻译：一种用于驱动设置在其上的器件或电路的驱动器电路，其包括并联连接的多个驱动晶体管，用于从多个组中选择一个或多个组的选择单元，其中驱动晶体管的功率基数为2，属于每个组的驱动晶体管的数量不同的驱动单元和属于由选择单元选择的组的驱动晶体管的驱动单元相同。

10. 发明申请

US20060022701A1 Termination circuit 有权
公开(公告)号：US20060022701A1
公开(公告)日：2006-02-02
申请号：US10982778
申请日：2004-11-08
申请人： Noriyuki Tokuhiro , Kunihiro Itoh
发明人： Noriyuki Tokuhiro , Kunihiro Itoh
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , H04L25/0298
摘要： A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.

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