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1. 发明授权

US06911734B2 Semiconductor device and electronic device 失效
公开(公告)号：US06911734B2
公开(公告)日：2005-06-28
申请号：US10391746
申请日：2003-03-20
申请人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
IPC分类号： H01L23/66 , H05K1/02 , H05K3/36 , H01L23/34
CPC分类号： H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

2. 发明授权

US06911733B2 Semiconductor device and electronic device 失效
标题翻译：半导体器件和电子器件
公开(公告)号：US06911733B2
公开(公告)日：2005-06-28
申请号：US10372898
申请日：2003-02-26
申请人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
IPC分类号： H01L23/66 , H05K1/02 , H05K3/36 , H01L23/34
CPC分类号： H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
摘要翻译：来自具有布置在其两侧的表面层信号引线和表面层GND引线的带状线段的高频信号经由封装衬底的信号表面层布线直接输入到半导体芯片，并通过焊料凸块电极。或者，来自半导体芯片的高频信号经由带状线路部分反向输出到外部。由于仅在封装衬底的整个表面层处的微带线传输高频信号，所以高频信号可以仅通过表层的微带线传输，而不需要通过通孔等。因此，可以不损失频率特性来发送高频信号，并且可以在高频率传输时以低损耗的方式发送高质量的高频信号。

3. 发明授权

US5661329A Semiconductor integrated circuit device including an improved separating groove arrangement 失效
标题翻译：半导体集成电路器件包括改进的分离槽布置
公开(公告)号：US5661329A
公开(公告)日：1997-08-26
申请号：US350944
申请日：1994-12-07
申请人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
发明人： Toshiro Hiramoto , Nobuo Tamba , Masami Usami , Takahide Ikeda , Kazuo Tanaka , Atsuo Watanabe , Satoru Isomura , Toshiyuki Kikuchi , Toru Koizumi
IPC分类号： H01L21/84 , H01L27/12 , H01L29/10 , H01L29/00 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/1079
摘要： A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.
摘要翻译：半导体集成电路器件包括分离形成为围绕要形成半导体元件的有源区的第一和第二沟槽的元件。此外，当从平面视图观察时，形成第三凹槽以围绕第一凹槽的至少一部分。在半导体集成电路器件中，硅层的有源区域和元件分离区域通过从硅层的主表面延伸到下面的绝缘层的分离槽彼此绝缘，并且被馈送有公共固定潜在。

4. 发明授权

US5428312A ECL interface circuit 失效
标题翻译： ECL接口电路
公开(公告)号：US5428312A
公开(公告)日：1995-06-27
申请号：US57827
申请日：1993-05-07
申请人： Keiichi Higeta , Satoru Isomura , Kazuhiro Akimoto
发明人： Keiichi Higeta , Satoru Isomura , Kazuhiro Akimoto
IPC分类号： G11C11/413 , H01L21/8244 , H01L27/11 , H03K19/003 , H03K19/086 , H03K19/0944
CPC分类号： H03K19/086 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device has a circuit construction which is devised with an output circuit for feeding an output current to an operating supply voltage in response to an output signal of a current switch circuit responding to an input signal. A constant current element for producing the operating current of the current switch circuit is fed with a constant voltage through a resistance element. A capacitor is coupled between the input of the constant current element and the operating supply voltage so that it constructs a time constant circuit together with the resistance element. The time constant circuit has a time constant set longer than the period of the output signal of the output circuit.
摘要翻译：半导体集成电路器件具有电路结构，该电路结构用于响应于电流开关电路响应于输入信号的输出信号，输出电路将输出电流馈送到工作电源电压。用于产生电流开关电路的工作电流的恒流元件通过电阻元件被馈送恒定电压。电容器耦合在恒流元件的输入端和工作电源电压之间，从而与电阻元件一起构成时间常数电路。时间常数电路具有比输出电路的输出信号的周期长的时间常数。

5. 发明授权

US4959704A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US4959704A
公开(公告)日：1990-09-25
申请号：US198311
申请日：1988-05-25
申请人： Satoru Isomura , Masato Iwabuchi , Katsumi Ogiue
发明人： Satoru Isomura , Masato Iwabuchi , Katsumi Ogiue
IPC分类号： H01L21/60 , H01L21/82 , H01L21/822 , H01L23/057 , H01L25/065 , H01L25/18 , H01L27/04 , H01L27/118
CPC分类号： H01L24/05 , H01L23/057 , H01L24/03 , H01L24/11 , H01L25/0652 , H01L25/18 , H01L27/118 , H01L27/11898 , H01L2224/0401 , H01L2224/04042 , H01L2224/05138 , H01L2224/11474 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/16145 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L24/12 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01021 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01045 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/351 , Y10S257/903
摘要： In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are canceled in differential sense circuits.
摘要翻译：在具有RAM的门阵列中，配置互连逻辑部分和门阵列的I / O单元电路的旁路信号线，以便在RAM的上方延伸。为了最小化相互干扰，从与旁路信号线相邻的层形成的信号线被设置成与直角信号线相交。此外，设置彼此平行延伸的不同层中的互连间距，使得差分感测电路中的噪声被消除。

6. 发明授权

US06636075B2 Semiconductor integrated circuit and its fabrication method 失效
公开(公告)号：US06636075B2
公开(公告)日：2003-10-21
申请号：US10060390
申请日：2002-02-01
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01P308
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

7. 发明授权

US5367490A Semiconductor integrated circuit device with two variable delay lines in writing circuit control 失效
标题翻译：半导体集成电路器件具有两个可变延迟线，用于写入电路控制
公开(公告)号：US5367490A
公开(公告)日：1994-11-22
申请号：US967133
申请日：1992-10-27
申请人： Kazuhiro Akimoto , Masami Usami , Katsumi Ogiue , Hiroshi Murayama , Hitoshi Abe , Masamori Kashiyama , Yoshikuni Kobayashi , Satoru Isomura , Kinya Mitsumoto
发明人： Kazuhiro Akimoto , Masami Usami , Katsumi Ogiue , Hiroshi Murayama , Hitoshi Abe , Masamori Kashiyama , Yoshikuni Kobayashi , Satoru Isomura , Kinya Mitsumoto
IPC分类号： G11C5/02 , G11C7/10 , G11C7/22 , H03K5/24 , G11C7/00
CPC分类号： G11C7/22 , G11C5/025 , G11C7/10 , H03K5/2418
摘要： Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.
摘要翻译：公开了一种半导体集成电路，其中用于与RAMS交换信号的逻辑电路，其中RAMS被布置在半导体芯片或基板上的中心处，根据信号的种类被分成多个逻辑电路，并且分开的逻辑电路是以使得与RAM的信号传输路径的距离最小化的方式设置在RAM周围，并且为了实现对RAMS的高速访问。

8. 发明授权

US5231138A Thermoplastic and elastomeric composition comprising a polyamide and a rubber component 失效
标题翻译：包含聚酰胺和橡胶组分的热塑性弹性体组合物
公开(公告)号：US5231138A
公开(公告)日：1993-07-27
申请号：US639438
申请日：1991-01-10
申请人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
发明人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
IPC分类号： C08L77/00
CPC分类号： C08L77/00
摘要： A thermoplastic and elastomeric composition comprising a polyamide resin and a rubber component, wherein the rubber component is dispersed in the form of crosslinked particles in the polyamide resin.
摘要翻译：一种包含聚酰胺树脂和橡胶组分的热塑性弹性体组合物，其中橡胶组分以聚酰胺树脂中交联颗粒的形式分散。

9. 发明授权

US4996264A Thermoplastic and elastomeric composition 失效
标题翻译：热塑性和弹性体组成
公开(公告)号：US4996264A
公开(公告)日：1991-02-26
申请号：US235863
申请日：1988-08-23
申请人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
发明人： Mitsuyoshi Aonuma , Tatsunosuke Suzuki , Satoru Isomura , Koichi Nishimura
IPC分类号： C08L9/02 , C08L21/00 , C08L33/04 , C08L33/06 , C08L33/08 , C08L77/00
CPC分类号： C08L77/00
摘要： A thermoplastic and elastomeric composition comprising a polyamide resin and a rubber component, wherein the rubber component is dispersed in the form of crosslinked particles in the polyamide resin.
摘要翻译：一种包含聚酰胺树脂和橡胶组分的热塑性弹性体组合物，其中橡胶组分以聚酰胺树脂中交联颗粒的形式分散。

10. 发明授权

US06937068B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06937068B2
公开(公告)日：2005-08-30
申请号：US10642138
申请日：2003-08-18
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L27/092 , H01L27/11 , H01L27/04
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
摘要翻译：具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

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