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1. 发明授权

US06911733B2 Semiconductor device and electronic device 失效
标题翻译：半导体器件和电子器件
公开(公告)号：US06911733B2
公开(公告)日：2005-06-28
申请号：US10372898
申请日：2003-02-26
申请人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
IPC分类号： H01L23/66 , H05K1/02 , H05K3/36 , H01L23/34
CPC分类号： H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
摘要翻译：来自具有布置在其两侧的表面层信号引线和表面层GND引线的带状线段的高频信号经由封装衬底的信号表面层布线直接输入到半导体芯片，并通过焊料凸块电极。或者，来自半导体芯片的高频信号经由带状线路部分反向输出到外部。由于仅在封装衬底的整个表面层处的微带线传输高频信号，所以高频信号可以仅通过表层的微带线传输，而不需要通过通孔等。因此，可以不损失频率特性来发送高频信号，并且可以在高频率传输时以低损耗的方式发送高质量的高频信号。

2. 发明授权

US06911734B2 Semiconductor device and electronic device 失效
公开(公告)号：US06911734B2
公开(公告)日：2005-06-28
申请号：US10391746
申请日：2003-03-20
申请人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
IPC分类号： H01L23/66 , H05K1/02 , H05K3/36 , H01L23/34
CPC分类号： H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

3. 发明授权

US6111322A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6111322A
公开(公告)日：2000-08-29
申请号：US858695
申请日：1997-05-19
申请人： Hideko Ando , Hiroshi Kikuchi , Toshihiko Sato , Tetsuya Hayashida
发明人： Hideko Ando , Hiroshi Kikuchi , Toshihiko Sato , Tetsuya Hayashida
IPC分类号： H01L21/56 , H01L21/60 , H01L23/12 , H01L23/36 , H01L23/373 , H01L23/433 , H05K3/30 , H05K3/34 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/32 , H01L21/563 , H01L23/3735 , H01L23/433 , H01L24/81 , H01L24/92 , H05K3/3436 , H01L2224/0401 , H01L2224/04026 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/81801 , H01L2224/92125 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15787 , H01L2924/16195 , H01L2924/351 , H05K2201/094 , H05K2201/09781 , H05K2201/2036 , H05K2203/047 , H05K3/303 , H05K3/3463 , Y02P70/613
摘要： An electrically reliable heat radiating package provided with a ball grid array (BGA) structure and a method of manufacturing the package are disclosed.A semiconductor chip is mounted on one surface of a ceramic wiring board via first solder bump electrodes and resin is filled in a gap area between the one surface of the wiring board and the principal surface of the semiconductor chip. A heat diffusing plate formed in a larger plane size than that of the semiconductor chip by aluminum nitride is arranged on the rear surface opposite to the principal surface of the semiconductor chip and soldered.Further, a radiating fin made of aluminum is provided on the heat diffusing plate and struck via silicone rubber in which a thermally conductive filler is includes.Further, the above first solder bump electrodes and second solder bump electrodes with a lower melting point than that of the solder used for the above soldering are formed on the rear surface of the above ceramic wiring board, and the above BGA package provided with a heat radiating structure is formed.This BGA package is mounted on a glass epoxy wiring board at low temperature.
摘要翻译：公开了一种具有球栅阵列（BGA）结构的电可靠性散热封装和制造封装的方法。半导体芯片通过第一焊料凸块电极安装在陶瓷布线板的一个表面上，并且树脂填充在布线板的一个表面和半导体芯片的主表面之间的间隙区域中。在与半导体芯片的主表面相对的后表面上布置有由氮化铝形成的具有比半导体芯片大的平面尺寸的热扩散板，并且被焊接。此外，在散热板上设置由铝制成的散热片，并通过其中包含导热填料的硅橡胶进行打击。此外，在上述陶瓷布线板的后表面上形成上述第一焊锡凸块电极和具有比用于上述焊接的焊料熔点低的熔点的第二焊料凸块电极，并且上述具有热量的BGA封装形成辐射结构。该BGA封装在低温下安装在玻璃环氧树脂布线板上。

4. 发明授权

US06433412B1 Semiconductor device and a method of manufacturing the same 有权
公开(公告)号：US06433412B1
公开(公告)日：2002-08-13
申请号：US09800589
申请日：2001-03-08
申请人： Hideko Ando , Hiroshi Kikuchi , Ikuo Yoshida , Toshihiko Sato , Tomo Shimizu
发明人： Hideko Ando , Hiroshi Kikuchi , Ikuo Yoshida , Toshihiko Sato , Tomo Shimizu
IPC分类号： H01L2302
摘要： A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 using face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions and for relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.

5. 发明授权

US06380621B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06380621B1
公开(公告)日：2002-04-30
申请号：US09543769
申请日：2000-04-05
申请人： Hideko Ando , Hiroshi Kikuchi , Toshihiko Sato , Tetsuya Hayashida
发明人： Hideko Ando , Hiroshi Kikuchi , Toshihiko Sato , Tetsuya Hayashida
IPC分类号： H01L2310
CPC分类号： H01L24/32 , H01L21/563 , H01L23/3735 , H01L23/433 , H01L24/81 , H01L24/92 , H01L2224/0401 , H01L2224/04026 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/81801 , H01L2224/92125 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/15787 , H01L2924/16195 , H01L2924/351 , H05K3/303 , H05K3/3436 , H05K3/3463 , H05K2201/094 , H05K2201/09781 , H05K2201/2036 , H05K2203/047 , Y02P70/613 , H01L2924/00
摘要： An electrically reliable heat radiating package provided with ball grid array (BGA) structure and a method of manufacturing the package are disclosed. In the concrete, a semiconductor chip is mounted on one surface of a ceramic wiring board via a first soldered bump electrode and resin is filled in a gap area between the one surface of the wiring board and the principal surface of the semiconductor chip. A heat diffusing plate formed in larger plane size than that of the semiconductor chip by aluminum nitride is arranged on the rear surface opposite to the principal surface of the semiconductor chip and soldered. Further, a radiating fin made of aluminum is provided on the heat diffusing plate and stuck via silicone rubber in which thermally conductive filler is included. Further, the above first soldered bump electrode and a second soldered bump electrode with a lower melting point than that of solder used for the above soldering are formed on the rear surface of the above ceramic wiring board and the above BGA package provided with heat radiating structure is formed. This BGA package is mounted on a glass epoxy wiring board at low temperature.
摘要翻译：公开了一种具有球栅阵列（BGA）结构的电可靠性散热封装和制造该封装的方法。具体而言，通过第一焊接突起电极和树脂将半导体芯片安装在陶瓷布线板的一个表面上填充在布线板的一个表面和半导体芯片的主表面之间的间隙区域中。在与半导体芯片的主表面相对的后表面上布置有由氮化铝形成的具有比半导体芯片更大的平面尺寸的热扩散板并焊接。此外，在散热片上设置由铝制成的散热片并通过其中包含导热填料的硅橡胶粘贴。此外，上述第一焊接凸块电极和熔点低于用于上述焊接的焊料熔点低的第二焊接凸块电极形成在形成陶瓷布线板以上的上述BGA封装，并具有散热结构。该BGA封装在低温下安装在玻璃环氧树脂布线板上。

6. 发明授权

US08076771B2 Semiconductor device having metal cap divided by slit 有权
标题翻译：具有由狭缝划分的金属帽的半导体器件
公开(公告)号：US08076771B2
公开(公告)日：2011-12-13
申请号：US12146864
申请日：2008-06-26
申请人： Hideko Ando
发明人： Hideko Ando
IPC分类号： H01L23/06 , H01L23/10 , H01L23/34 , H01L23/12
CPC分类号： H01L23/492 , H01L23/3675 , H01L23/40 , H01L24/31 , H01L24/83 , H01L2224/16225 , H01L2224/73153 , H01L2224/73253 , H01L2224/83192 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/15312 , H01L2924/16152 , H01L2924/1616 , H01L2924/351 , Y10S257/924 , H01L2924/00
摘要： In order to reduce a thermal stress applied by a metal cap to a semiconductor chip: a semiconductor chip (2) is bonded to a flat portion (11) of a metal cap (1); side wall portions of the metal cap (1) serve as external connection terminals (13); and a slit (7) is formed in the metal cap (1) so as to cross the semiconductor chip (2), so a bonding region between the semiconductor chip (2) and the metal cap (1) is divided into small bonding regions to reduce thermal stresses applied to the respective bonding regions. Therefore, peeling can be prevented in respective bonding regions, whereby a small-size semiconductor device in which the semiconductor chip is bonded to the metal cap with improved bonding reliability is obtained.
摘要翻译：为了将由金属盖施加的热应力减小到半导体芯片：将半导体芯片（2）接合到金属盖（1）的平坦部分（11）上; 金属盖（1）的侧壁部分用作外部连接端子（13）; 并且在所述金属盖（1）中形成有与所述半导体芯片（2）交叉的狭缝（7），所以将所述半导体芯片（2）与所述金属盖（1）的接合区域分割成小的接合区域以减少施加到各个接合区域的热应力。因此，可以在各个接合区域中防止剥离，从而获得其中半导体芯片与金属盖接合并提高接合可靠性的小尺寸半导体器件。

7. 发明授权

US06747356B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06747356B2
公开(公告)日：2004-06-08
申请号：US10386441
申请日：2003-03-13
申请人： Hideko Ando , Seiji Miyamoto
发明人： Hideko Ando , Seiji Miyamoto
IPC分类号： H01L2348
CPC分类号： H01L23/66 , H01L23/49822 , H01L2224/16 , H01L2224/16235 , H01L2924/15173 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H05K1/024 , H05K1/0298 , H05K3/4602 , H05K2201/0191
摘要： Control of the characteristic impedance of wirings is performed with high accuracy. Relative to a first wiring of a second wiring layer arranged above a through hole of a core layer in a package board, the thickness of a first insulating layer between a first wiring layer on the surface of the core layer and the second wiring layer is made large, and the thickness of a second insulating layer between a third wiring layer that is a plane layer on the side of opposite thereto and the second wiring layer is made small, thereby allowing for: reducing the impedance coupling between the power plane of the first wiring layer on the surface of the core layer and the first and second wirings; reinforcing the impedance coupling between the power plane of the third wiring layer on the side opposite thereto and the first and second wirings; and achieving the reduction of the difference in the characteristic impedance between the first wiring arranged just above the through hole and the second wiring arranged away from just above the through hole.
摘要翻译：高精度地进行布线特性阻抗的控制。相对于在封装基板中配置在芯层的通孔上方的第二布线层的第一布线，使得在芯层表面上的第一布线层和第二布线层之间的第一绝缘层的厚度并且在与其相对侧的平面层的第三布线层和第二布线层之间的第二绝缘层的厚度变小，从而允许：降低第一布线层的第一布线层与第二布线层之间的阻抗耦合。芯层表面上的布线层和第一和第二布线; 加强第三布线层的与其相反的一侧的电源面与第一和第二布线之间的阻抗耦合; 并且实现了布置在通孔正上方的第一布线与远离通孔正上方布置的第二布线之间的特性阻抗差的减小。

8. 发明授权

US07035081B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07035081B2
公开(公告)日：2006-04-25
申请号：US10478800
申请日：2002-05-28
申请人： Tatsuya Nagata , Seiji Miyamoto , Hideko Ando
发明人： Tatsuya Nagata , Seiji Miyamoto , Hideko Ando
IPC分类号： H01G4/228
CPC分类号： H01L23/49822 , H01L23/49827 , H01L2224/16 , H01L2224/16225 , H01L2924/01078 , H01L2924/15311 , H01L2924/3011 , H05K1/0216 , H05K1/112 , H05K1/115 , H05K3/4602 , H05K2201/09536 , H05K2201/09781 , H05K2201/10674
摘要： The invention eliminates a need to increase a size of a semiconductor device and reduces occurrence of noise. A semiconductor device of the invention includes: a base (5) having front layers (9, 11) provided on respective sides of a core layer (7) formed by a printed circuit board, and a semiconductor chip (1) mounted on the base (5), wherein the semiconductor chip (1) is joined to one (9) of the front layers by using a joining member (3), and the other front layer (11) has a plurality of external terminals (55) arranged thereon, and the core layer (7) has a plurality of through-holes (41, 43, 45, 75, 77) formed therein to electrically connect the semiconductor chip (1) to the plurality of external terminals (55) together, and the plurality of through-holes (41, 43, 45, 75, 77) include a plurality of arrayed through-holes (41, 43, 45) arranged correspondingly to the arrangement of the plurality of external terminals (55) and one or more additional through-holes (75, 77) formed between the plurality of arrayed through-holes (41, 43, 45).
摘要翻译：本发明不需要增加半导体器件的尺寸并减少噪声的发生。本发明的半导体器件包括：基底（5），其具有设置在由印刷电路板形成的芯层（7）的相应侧上的前层（9,11）和安装在基底上的半导体芯片（1）（5），其中所述半导体芯片（1）通过使用接合部件（3）接合到所述前层中的一个（9），并且所述另一个前层（11）具有布置在其上的多个外部端子（55），芯层（7）具有形成在其中的多个通孔（41,43,45,75,77），以将半导体芯片（1）与多个外部端子（55）电连接在一起，并且多个通孔（41,43,45,75,77）包括与多个外部端子（55）的布置相对应布置的多个排列的通孔（41,43,45）和一个或多个附加的形成在多个排列的通孔（41,43,45）之间的通孔（75,77）。

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