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1. 发明授权

US08547424B2 Endoscope system and lens unit 有权
标题翻译：内窥镜系统和镜头单元
公开(公告)号：US08547424B2
公开(公告)日：2013-10-01
申请号：US12254479
申请日：2008-10-20
申请人： Hiroshi Ishii , Seiji Iwasaki , Masahiro Kawauchi , Hideaki Ishihara , Susumu Takahashi , Shinichi Nakamura , Azusa Noguchi , Hideyasu Takato , Tsutomu Sasamoto
发明人： Hiroshi Ishii , Seiji Iwasaki , Masahiro Kawauchi , Hideaki Ishihara , Susumu Takahashi , Shinichi Nakamura , Azusa Noguchi , Hideyasu Takato , Tsutomu Sasamoto
IPC分类号： A61B1/06 , A61B1/04
CPC分类号： G02B23/26 , A61B1/00096 , A61B1/00186 , A61B1/043 , A61B1/045 , A61B1/063 , A61B1/0638 , A61B1/0646 , A61B5/0071 , A61B5/0084 , G02B23/2438 , G02B23/2469 , G03B9/02 , G03B15/05 , G03B2215/0564 , G03B2215/0575
摘要： An endoscope system has a light source apparatus and an endoscope including an illumination optical system and an objective optical system. At least the objective optical system of the endoscope is provided with an adjustable diaphragm, and in a light path in one of the light source apparatus, the illumination optical system, and the objective optical system, an insertable/retractable filter for observation for special light is provided. The adjustable diaphragm performs a closing operation or an opening operation only when the filter for observation for special light is inserted into the light path.
摘要翻译：内窥镜系统具有包括照明光学系统和物镜光学系统的光源装置和内窥镜。至少内窥镜的物镜光学系统设置有可调节光阑，并且在光源装置，照明光学系统和物镜光学系统之一中的光路中，用于观察特殊光的可插入/可缩回过滤器被提供。仅当用于观察特殊光的过滤器插入光路中时，可调节膜片才执行关闭操作或打开操作。

2. 发明授权

US08988077B2 Battery condition detection sensor 有权
标题翻译：电池状态检测传感器
公开(公告)号：US08988077B2
公开(公告)日：2015-03-24
申请号：US13387735
申请日：2011-03-28
申请人： Hideaki Ishihara
发明人： Hideaki Ishihara
IPC分类号： G01N27/416 , H01M2/30 , G01R31/36 , H01M10/42 , H01R11/28 , G01R1/20 , H01R13/66
CPC分类号： H01M2/30 , G01R1/203 , G01R31/3696 , H01M10/425 , H01R11/287 , H01R13/6683 , H01R2201/26
摘要： A battery condition detection sensor (1) for measuring characteristics of a battery (101) includes an electrically conductive battery post terminal (12) and a shunt resistor (13). The battery post terminal (12) is mounted to a battery post (102) provided in the battery (101). The shunt resistor (13) is electrically connected to the battery post terminal (12). The shunt resistor (13) is configured such that a connection terminal (52) of a wire harness (51) can be fixed thereto. The shunt resistor (13) has a rotation-blocking portion (inner walls of the insertion holes (15a, 15b)) for blocking rotation of the connection terminal (52).
摘要翻译：用于测量电池（101）的特性的电池状态检测传感器（1）包括导电电池柱端子（12）和分流电阻器（13）。电池柱端子（12）安装在设置在电池（101）中的电池支柱（102）上。分流电阻器（13）电连接到电池柱端子（12）。分流电阻器（13）被配置为使得线束（51）的连接端子（52）能够被固定到其上。分流电阻器（13）具有用于阻止连接端子（52）的旋转的旋转阻挡部（插入孔的内壁（15a，15b））。

3. 发明授权

US08587279B2 Power conversion apparatus 有权
标题翻译：电力转换装置
公开(公告)号：US08587279B2
公开(公告)日：2013-11-19
申请号：US13409269
申请日：2012-03-01
申请人： Fan Wang , Tomonori Kimura , Atsushi Kobayashi , Hideaki Ishihara , Masakiyo Horie
发明人： Fan Wang , Tomonori Kimura , Atsushi Kobayashi , Hideaki Ishihara , Masakiyo Horie
IPC分类号： G05F1/00
CPC分类号： H03K17/162 , H02M3/1588 , H02M2001/342 , H02M2001/344 , H03K2217/0036 , Y02B70/1466 , Y02B70/1491
摘要： A power conversion apparatus includes main circuits, in which switching elements are connected in parallel with diodes, respectively. An auxiliary circuit, which is formed of a series-connected second switching element and a capacitor, is connected in parallel with the diode operating as a freewheeling diode. The switching element of the main circuit, which is opposite to the auxiliary circuit, is set to turn on at a reference time. The second switching element of the auxiliary circuit is set to turn on in advance of the reference time by an interval of a discharging time period of the capacitor in a dead time period.
摘要翻译：电力转换装置包括主电路，其中开关元件分别与二极管并联连接。由串联连接的第二开关元件和电容器构成的辅助电路与作为续流二极管工作的二极管并联连接。与辅助电路相反的主电路的开关元件设定为在参考时间导通。辅助电路的第二开关元件被设置为在死区时间内以电容器的放电时间段的间隔在基准时间之前接通。

4. 发明授权

US07982512B2 Communication system communication device and method for determining duty ratio of PWM control 有权
标题翻译：通信系统通信装置及确定PWM控制占空比的方法
公开(公告)号：US07982512B2
公开(公告)日：2011-07-19
申请号：US12585673
申请日：2009-09-22
申请人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Katsutoyo Misawa , Masato Rinnai , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： H03K3/017
CPC分类号： H04L12/403 , H04L12/10 , H04L12/40045 , H04L12/66 , H04L2012/40273
摘要： A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication.
摘要翻译：通信系统包括：主人; 多个奴隶; 以及用于在主机和多个从机之间耦合的总线，以便在主机和多个从机之间异步通信。主人在供电期间向公共汽车供电。主器件或从器件在数据传输周期内通过总线驱动总线以发送一位数据。连续执行电源周期和数据传输周期，使得在主机和多个从机之间执行由多个一比特周期提供的数据通信。主人精细地改变数据通信中的通信频率。主机将数据通信中总线的驱动级别改变在预定的可接受范围内。

5. 发明申请

US20100017585A1 Microcomputer and encoding system for instruction code and CPU 有权
标题翻译：微机和编码系统的指令代码和CPU
公开(公告)号：US20100017585A1
公开(公告)日：2010-01-21
申请号：US12585781
申请日：2009-09-24
申请人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
发明人： Naoki Ito , Masahiro Kamiya , Hideaki Ishihara
IPC分类号： G06F9/46 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/30003 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/30072 , G06F9/30094 , G06F9/30145 , G06F9/30167 , G06F9/30185 , G06F9/3552 , G06F11/0721 , G06F11/0751
摘要： A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable as a timer counter, a peripheral function instruction is described in the specific task, the peripheral function instruction is set so as to indicate one or more general-purpose registers as an operand. The CPU executes the peripheral function instruction as one instruction and achieves information needed to execute the instruction by a general-purpose register and stores the execution result into the general-purpose registers. An instruction code encoding system includes an operation code and plural operands for indicating operation targets of an instruction in an instruction code and executing an instruction indicated by the operation code on the operation targets. When the operation targets indicated by the plural operands are set to a combination in which an execution result does not vary, the processing corresponding to an instruction different is executed.
摘要翻译：一种可以分时和并行地处理多个任务的微计算机，其中由任务之一描述的多个程序中的一个被描述为循环的特定任务，其中程序地址的增量是固定的，程序计数器可用作定时器计数器，在特定任务中描述外设功能指令，外设功能指令被设置为指示一个或多个通用寄存器作为操作数。 CPU作为一个指令执行外围功能指令，并实现由通用寄存器执行指令所需的信息，并将执行结果存储到通用寄存器中。指令代码编码系统包括操作代码和用于指示指令代码中的指令的操作目标的多个操作数，并且执行由操作对象上的操作代码指示的指令。当由多个操作数指示的操作目标被设置为执行结果不变化的组合时，执行与不同指令相对应的处理。

6. 发明申请

US20090204841A1 Periodic signal processing apparatus 有权
标题翻译：周期信号处理装置
公开(公告)号：US20090204841A1
公开(公告)日：2009-08-13
申请号：US12320800
申请日：2009-02-05
申请人： Akimasa Niwa , Masahiro Kamiya , Hideaki Ishihara , Yoshinori Teshima
发明人： Akimasa Niwa , Masahiro Kamiya , Hideaki Ishihara , Yoshinori Teshima
IPC分类号： G06F13/42
CPC分类号： G01D3/022
摘要： A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.
摘要翻译：用于处理从信号源输出的周期信号的信号处理装置具有中央处理单元和任务切换定时器。中央处理单元并行执行包括信号处理任务的多个任务。在信号处理任务中，中央处理单元在执行同步处理之后开始对周期信号进行处理以与周期信号同步，在完成同步处理之后将任务切换定时器设定到预定时间，完成同步处理后的中央处理单元。任务切换定时器在到期前立即停止中央处理单元的中断。任务切换定时器在到期时向中央处理单元输出任务切换信号，使得中央处理单元切换到信号处理任务。

7. 发明申请

US20090096504A1 Data reception apparatus and microcomputer having the same 有权
标题翻译：数据接收装置和具有该数据接收装置的微型计算机
公开(公告)号：US20090096504A1
公开(公告)日：2009-04-16
申请号：US12285581
申请日：2008-10-09
申请人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： H03K3/011
CPC分类号： H03L1/025 , H03L1/026 , H03L7/06
摘要： A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.
摘要翻译：数据接收装置包括：振荡电路，其根据周期设定值对来自CR振荡器的振荡信号进行倍数或分频，并输出与所乘的或分频的振荡信号对应的时钟信号; 温度检测器; 记忆时钟周期设定元件，其从存储器读取与温度对应的周期设定值，并将该周期设定值输入到振荡电路中; 接收器，接收由时钟信号定义的数据信号; 测量元件，通过对时钟信号进行计数来测量数据信号的单位比特长度; 以及校正元件，其基于时钟信号的计数值和与单位比特长度对应的基准周期的基准计数值来校正周期设定值，并且以修正的周期设定值重写周期设定值。

8. 发明授权

US07467294B2 Microcomputer with mode decoder operable upon receipt of either power-on or external reset signal 有权
标题翻译：具有模式解码器的微计算机，在接收到电源接通或外部复位信号时可操作
公开(公告)号：US07467294B2
公开(公告)日：2008-12-16
申请号：US11270447
申请日：2005-11-10
申请人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
发明人： Toshihiko Matsuoka , Naoki Ito , Hideaki Ishihara , Yasuyuki Ishikawa
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.
摘要翻译：微型计算机包括多个操作模式选择端子，用于选择多个操作模式的数据。多个操作模式选择端子被设计为可用作通用输入端子或输出端子。解码器将对多个操作模式选择端子设置的数据进行解码，并根据选择的操作模式输出用于切换内部功能的模式信号。定时信号输出单元向解码器输出用于使解码器执行解码操作的定时信号。当上电复位和外部控制的复位中的至少一个从活动状态变为非活动状态时，定时信号输出单元输出定时信号。

9. 发明授权

US07356719B2 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US07356719B2
公开(公告)日：2008-04-08
申请号：US11357372
申请日：2006-02-21
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/26
CPC分类号： G06F1/04
摘要： In an EEPROM of a microcomputer, data is stored for determining a communication rate CMR for fixing the data transmission time of one frame managed by a communication circuit on the basis of an oscillation output characteristic of a CR oscillating circuit that varies in accordance with temperature. CPU reads out data stored in EEPROM in accordance with the temperature detected by a temperature detecting circuit, and sets the determined communication CMR into the communication circuit.
摘要翻译：在微型计算机的EEPROM中，存储数据，用于根据根据温度变化的CR振荡电路的振荡输出特性确定用于固定由通信电路管理的一帧的数据传输时间的通信速率CMR。 CPU根据温度检测电路检测到的温度读出存储在EEPROM中的数据，并将确定的通信CMR设置到通信电路中。

10. 发明授权

US07248092B2 Clamp circuit device 有权
标题翻译：钳位电路器件
公开(公告)号：US07248092B2
公开(公告)日：2007-07-24
申请号：US11073564
申请日：2005-03-08
申请人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
发明人： Katsutoyo Misawa , Yasuyuki Ishikawa , Akira Suzuki , Yoshinori Teshima , Hideaki Ishihara , Toshiharu Muramatsu
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5−Vtn] when an excessive voltage of negative polarity is applied.
摘要翻译：在钳位电路器件中，参考电压由FET，电阻器和FET的串联电路构成。通过执行这些参考电压的加法和减法以及由带隙基准电路产生的参考电压来建立FET的栅极电位。钳位电路器件通过将一个FET的源极与其电源连接在一起而将另一个FET的源极与地线连接到控制IC单元的输入端而构成。因此，当施加过大的正极性电压到输入端子时，输入电压被钳位到[V 4+ Vtp]，并且当施加负极性的过大电压时，输入电压被钳位到[V 5- Vtn] 。

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