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1. 发明专利

JP2005021591A Healthy footwear 有权
标题翻译：健康鞋
公开(公告)号：JP2005021591A
公开(公告)日：2005-01-27
申请号：JP2003270554
申请日：2003-07-03
申请人： Toshihiko Matsuoka , 敏彦松岡
发明人： MATSUOKA TOSHIHIKO
IPC分类号： A43B13/14 , A43B7/14
摘要： PROBLEM TO BE SOLVED: To provide healthy footwear which promotes health of a body by affecting tiptoes intensely and moving muscles of the entire body and a bone structure when a user walks, has a simple structure, and is manufactured at a low cost.
SOLUTION: A tier part 16 in which a part from the base of the toes to the tiptoes is raised by a step to place at least one toe while flexing the toe upward is provided on the upper surface side of a bottom part (12) for placing the foot. The toes F flexed by the tier part 16 is tensioned intensely every time the weight is shifted to the side of the tiptoes as the user walks.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供健康的鞋类，其通过在用户行走时强烈地影响脚趾并且移动整个身体的肌肉和骨骼结构来促进身体的健康，具有简单的结构，并且以低成本制造。解决方案：一层部分16，其中从脚趾的基部到脚尖的部分在向上弯曲的情况下通过台阶放置至少一个脚趾而设置在底部的上表面侧（ 12）用于放置脚。当用户走路时，每次重量偏移到脚尖侧时，由层部16弯曲的脚趾F被强烈张紧。版权所有（C）2005，JPO＆NCIPI

2. 发明授权

US08762612B2 Communication slave 有权
标题翻译：通讯从站
公开(公告)号：US08762612B2
公开(公告)日：2014-06-24
申请号：US13032040
申请日：2011-02-22
申请人： Yoshie Sugiura , Toshihiko Matsuoka
发明人： Yoshie Sugiura , Toshihiko Matsuoka
IPC分类号： G06F3/00 , G06F13/00 , G06F1/00
CPC分类号： H04L12/403
摘要： A communication slave used in a communication network system includes a control device, a capacitive element, a voltage determining portion, and a time measuring portion. The control device controls communication with a master. The capacitive element is coupled between a high-potential side bus and a low-potential side bus. The voltage determining portion determines whether a voltage between the buses exceeds a threshold voltage. The time measuring portion measures a time from when a charge of the capacitive element through the buses is started to when the voltage determining portion determines that the voltage exceeds the threshold voltage. The control device sets an ID value for communicating with the master based on a length of the time measured by the time measuring portion.
摘要翻译：在通信网络系统中使用的通信从站包括控制设备，电容元件，电压确定部分和时间测量部分。控制装置控制与主机的通信。电容元件耦合在高电位侧总线和低电位侧总线之间。电压确定部分确定总线之间的电压是否超过阈值电压。时间测量部分测量从电容元件通过总线的充电开始到电压确定部分确定电压超过阈值电压的时间。控制装置基于由时间测量部测量的时间长度来设定用于与主机通信的ID值。

3. 发明授权

US08467441B2 Pulse width modulation communication system 有权
标题翻译：脉宽调制通信系统
公开(公告)号：US08467441B2
公开(公告)日：2013-06-18
申请号：US13157906
申请日：2011-06-10
申请人： Hideo Sawaoka , Yasuaki Makino , Toshihiko Matsuoka
发明人： Hideo Sawaoka , Yasuaki Makino , Toshihiko Matsuoka
IPC分类号： H03K7/08
CPC分类号： H03K7/08 , H04L25/4902
摘要： In a PWM communication system, a sensor unit transmits as reference pulses transmission signals, which exhibit duty cycles of 100% and 0%, respectively, prior to transmission of a transmission signal, which has data items compressed thereinto by a signal processing circuit. An input capture circuit of an ECU measures the duty time and the PWM cycle of the transmission signal according to a timer clock of a timer circuit. A signal processing circuit of the ECU produces a duty cycle correction factor k based on the measured duty times and PWM cycles of the reference pulses, produces receiving data based on the duty time and the PWM cycle of the transmission signal, and the duty cycle correction factor, and separates the receiving data into sensor output values of a pressure sensor and a temperature sensor.
摘要翻译：在PWM通信系统中，传感器单元作为参考脉冲发送传输信号，传输信号在传输信号之前分别表现出占有率为100％和0％的传输信号，传输信号具有由信号处理电路压缩的数据项。 ECU的输入捕捉电路根据定时器电路的定时器时钟来测量发送信号的占空比和PWM周期。 ECU的信号处理电路基于测量的占空比时间和参考脉冲的PWM周期产生占空比校正因子k，基于发送信号的占空比和PWM周期产生接收数据，并且占空比校正因子，并将接收数据分离成压力传感器和温度传感器的传感器输出值。

4. 发明授权

US07634547B2 Communication network system, and ID allocating method and ID setting method for communication network system 有权
标题翻译：通信网络系统，通信网络系统的ID分配方法和ID设置方法
公开(公告)号：US07634547B2
公开(公告)日：2009-12-15
申请号：US11004971
申请日：2004-12-07
申请人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
发明人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
IPC分类号： G06F15/16 , G06F15/177
CPC分类号： H04L61/2038 , H04L29/12254
摘要： When each slave ECU is powered on and activated while connected to a communication network through a harness, it reads out divided voltage potential applied by voltage dividing resistors in each ID determining signal line, and allows reception of a data packet transmitted from control ECU when a wait time corresponding to the divided voltage potential elapses. The control ECU successively transmits a data packet containing as a main body ID data to be allocated to each slave ECU, and each slave ECU sets ID data transmitted as its own ID.
摘要翻译：当每个从ECU在通过线束连接到通信网络时通电并激活时，它读出每个ID确定信号线中的分压电阻施加的分压电压，并允许接收从控制ECU发送的数据分组等待时间对应于分压后的电压电位。控制ECU依次发送包含要分配给每个从ECU的主体ID数据的数据分组，并且每个从ECU设置作为其自身ID发送的ID数据。

5. 发明授权

US07554415B2 Microcomputer including a CR oscillator circuit 有权
标题翻译：微电脑包括CR振荡电路
公开(公告)号：US07554415B2
公开(公告)日：2009-06-30
申请号：US11640876
申请日：2006-12-19
申请人： Toshihiko Matsuoka , Hideaki Ishihara
发明人： Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： H03B5/24 , H03K3/02 , H03L1/02 , H03L7/06
CPC分类号： H03L1/026 , H03L1/027 , H03L7/0996 , H03L7/16
摘要： A microcomputer includes an oscillator for generating a clock signal having a frequency by using a CR circuit, a multiplier for outputting the clock signal having a multiplied frequency relative to the frequency generated by the oscillator based on data from an external source, a temperature detection unit for detecting temperature at a proximity of the CR circuit, a storage unit for storing data that enables the multiplied frequency of the clock signal in an output from the multiplier to have a constant value based on a temperature-dependent oscillation characteristic of the oscillator, and a control unit for setting a multiplication value for generating the multiplied frequency of the clock signal to the multiplier based on the data in the storage unit that is correlated to the temperature detected by the temperature detection unit.
摘要翻译：微型计算机包括用于通过使用CR电路产生具有频率的时钟信号的振荡器，用于根据来自外部源的数据输出相对于由振荡器产生的频率具有相乘频率的时钟信号的乘法器，温度检测单元用于检测所述CR电路附近的温度，存储单元，用于存储使所述乘法器的输出中的时钟信号的倍频能够基于所述振荡器的温度相关振荡特性而具有恒定值的数据;以及控制单元，用于根据与由温度检测单元检测到的温度相关的存储单元中的数据，将用于产生时钟信号的倍频的乘法值设置到乘法器。

6. 发明授权

US06760789B2 Microcomputer having temporary storage for received data and method of processing received data 有权
标题翻译：微型计算机具有接收数据的临时存储和处理接收数据的方法
公开(公告)号：US06760789B2
公开(公告)日：2004-07-06
申请号：US10022796
申请日：2001-12-20
申请人： Yoichi Fujita , Hiroshi Matsuda , Toshihiko Matsuoka
发明人： Yoichi Fujita , Hiroshi Matsuda , Toshihiko Matsuoka
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： A first receiving message is stored in a message box and a CPU reads the first receiving message from the message box. Meanwhile, a second receiving message is once stored in the message box and thereafter transferred directly to a RAM by a DMA controller. The number of times of transfer operation is restricted with an upper limit value. The CPU does not read the second receiving message from the message box but from the RAM and executes the processes based on the message. Generation of failure in the receiving data fetching processes is reduced without physical expansion of the storage regions of the message box.
摘要翻译：第一接收消息存储在消息框中，CPU从消息框中读取第一接收消息。同时，第二接收消息一旦存储在消息框中，然后由DMA控制器直接传送到RAM。传送操作次数受限于上限值。 CPU不会从消息框中读取第二个接收消息，而是从RAM中读取第二个接收消息，并根据消息执行进程。在消息框的存储区域的物理扩展的情况下，减少接收数据获取处理中的故障的产生。

7. 发明申请

US20090009211A1 Microcomputer and functional evaluation chip 有权
标题翻译：微电脑和功能评估芯片
公开(公告)号：US20090009211A1
公开(公告)日：2009-01-08
申请号：US12155017
申请日：2008-05-29
申请人： Naoki Ito , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
发明人： Naoki Ito , Hideaki Ishihara , Toshihiko Matsuoka , Katsutoyo Misawa
IPC分类号： H03K19/00
CPC分类号： G06F11/26
摘要： A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation mode; a clock input terminal; a data terminal through which serial data is inputted synchronously with a serial clock signal applied to the clock input terminal; a serial-to-parallel conversion unit that converts the serial data into parallel data and stores the parallel data in an input data buffer; and a switching means that switches to a state that a CPU can access to the input data buffer in a test mode. In the test mode, test instruction data is capable of being inputted from an external circuit.
摘要翻译：根据操作模式起作用的微计算机包括：对施加到模式设置终端的信号中的电平变化次数进行计数的模式计数器; 解码模式计数器的输出数据以输出表示一种操作模式的模式信号的模式解码器; 时钟输入端子; 数据终端，串行数据与施加到时钟输入端的串行时钟信号同步输入; 串行到并行转换单元，将串行数据转换为并行数据，并将并行数据存储在输入数据缓冲器中; 以及切换装置，切换到CPU能够以测试模式访问输入数据缓冲器的状态。在测试模式下，能够从外部电路输入测试指令数据。

8. 发明授权

US07444529B2 Microcomputer having rewritable nonvolatile memory 失效
标题翻译：微计算机具有可重写的非易失性存储器
公开(公告)号：US07444529B2
公开(公告)日：2008-10-28
申请号：US11238106
申请日：2005-09-29
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/128
摘要： A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.
摘要翻译： CPU在转移到休眠模式时，通过低功耗控制电路中止振荡电路和倍频器电路的振荡操作。闪光电源电路中断电路或中断的振荡操作或响应于恢复停止的操作来恢复外部电源的供应。当CPU被切换到睡眠模式时，倍频电路保持设定的振荡控制条件。当振荡操作要恢复时，基于所保持的振荡控制条件进行操作。当睡眠模式复位时，CPU访问掩码ROM，并立即读出在唤醒之后要执行的控制程序。

9. 发明申请

US20060069933A1 Microcomputer having rewritable nonvolatile memory 失效
标题翻译：微计算机具有可重写的非易失性存储器
公开(公告)号：US20060069933A1
公开(公告)日：2006-03-30
申请号：US11238106
申请日：2005-09-29
申请人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
发明人： Toshihiko Matsuoka , Hideaki Ishihara , Yukari Sugiura
IPC分类号： G06F1/26
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/128
摘要： A CPU, when shifting to a sleep mode, discontinues the oscillating operations of an oscillation circuit and of a frequency multiplier circuit through a low power consumption control circuit. A flash power source circuit discontinues the oscillating operations of the circuits or interrupts or resumes the supply of an external power source in response to resumption of the halted operation. When the CPU is to be shifted to the sleep mode, the frequency multiplier circuit holds the set oscillation control conditions. When the oscillating operation is to be resumed, operates based on the oscillation control conditions that are held. When the sleep mode is reset, the CPU makes access to the mask ROM and immediately reads out a control program that is to be executed right after the wakeup.
摘要翻译： CPU在转移到休眠模式时，通过低功耗控制电路中止振荡电路和倍频器电路的振荡操作。闪光电源电路中断电路或中断的振荡操作或响应于恢复停止的操作来恢复外部电源的供应。当CPU被切换到睡眠模式时，倍频电路保持设定的振荡控制条件。当振荡操作要恢复时，基于所保持的振荡控制条件进行操作。当睡眠模式复位时，CPU访问掩码ROM，并立即读出在唤醒之后要执行的控制程序。

10. 发明申请

US20050152388A1 Communication network system, and ID allocating method and ID setting method for communication network system 有权
标题翻译：通信网络系统，通信网络系统的ID分配方法和ID设置方法
公开(公告)号：US20050152388A1
公开(公告)日：2005-07-14
申请号：US11004971
申请日：2004-12-07
申请人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
发明人： Yukari Ishiguro , Hideaki Ishihara , Toshihiko Matsuoka
IPC分类号： H04L12/28 , H04L29/12
CPC分类号： H04L61/2038 , H04L29/12254
摘要： When each slave ECU is powered on and activated while connected to a communication network through a harness, it reads out divided voltage potential applied by voltage dividing resistors in each ID determining signal line, and allows reception of a data packet transmitted from control ECU when a wait time corresponding to the divided voltage potential elapses. The control ECU successively transmits a data packet containing as a main body ID data to be allocated to each slave ECU, and each slave ECU sets ID data transmitted as its own ID.
摘要翻译：当每个从ECU在通过线束连接到通信网络时通电并激活时，它读出每个ID确定信号线中的分压电阻施加的分压电压，并允许接收从控制ECU发送的数据分组等待时间对应于分压后的电压电位。控制ECU依次发送包含要分配给每个从ECU的主体ID数据的数据分组，并且每个从ECU设置作为其自身ID发送的ID数据。

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