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1. 发明授权

US08559462B2 Synchronization signal detection apparatus 有权
标题翻译：同步信号检测装置
公开(公告)号：US08559462B2
公开(公告)日：2013-10-15
申请号：US13029430
申请日：2011-02-17
申请人： Kazushi Matsuo , Toshihiko Matsuoka
发明人： Kazushi Matsuo , Toshihiko Matsuoka
IPC分类号： H04L7/00 , H04J3/24
CPC分类号： H04L12/403 , H04L7/046
摘要： A synchronization signal detection apparatus includes a temporary synchronization signal detector and a final synchronization signal detector. A header of a synchronization signal has at least M successive bits of a first level, where M is an integer more than the Nth power of 2, and N is a positive integer. The synchronization signal has alternating bits starting with a second level. The temporary synchronization signal detector detects the Nth power of 2 successive bits of the first level as a temporary synchronization signal when receiving the Nth power of 2 successive bits of the first level before receiving the alternating bits. The final synchronization signal detector determines that the detected temporary synchronization signal is the header when receiving the at least M successive bits of the first level.
摘要翻译：同步信号检测装置包括临时同步信号检测器和最终同步信号检测器。同步信号的标题具有至少M个第一级的连续位，其中M是大于第N次幂2的整数，N是正整数。同步信号具有以第二电平开始的交替位。临时同步信号检测器在接收到交替位之前接收到第一电平的2个连续位的第N个功率时，将第一电平的2个连续位的第N个功率作为临时同步信号进行检测。当接收到第一级的至少M个连续位时，最终同步信号检测器确定检测到的临时同步信号是标题。

2. 发明授权

US08099621B2 Data reception apparatus and microcomputer having the same 有权
标题翻译：数据接收装置和具有该数据接收装置的微型计算机
公开(公告)号：US08099621B2
公开(公告)日：2012-01-17
申请号：US12285581
申请日：2008-10-09
申请人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： G06F1/04
CPC分类号： H03L1/025 , H03L1/026 , H03L7/06
摘要： A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.
摘要翻译：数据接收装置包括：振荡电路，其根据周期设定值对来自CR振荡器的振荡信号进行倍数或分频，并输出与所述相乘或分频振荡信号对应的时钟信号; 温度检测器; 记忆时钟周期设定元件，其从存储器读取与温度对应的周期设定值，并将该周期设定值输入到振荡电路中; 接收器，接收由时钟信号定义的数据信号; 测量元件，通过对时钟信号进行计数来测量数据信号的单位比特长度; 以及校正元件，其基于时钟信号的计数值和与单位比特长度对应的基准周期的基准计数值来校正周期设定值，并且以修正的周期设定值重写周期设定值。

3. 发明申请

US20110206067A1 SYNCHRONIZATION SIGNAL DETECTION APPARATUS 有权
标题翻译：同步信号检测装置
公开(公告)号：US20110206067A1
公开(公告)日：2011-08-25
申请号：US13029430
申请日：2011-02-17
申请人： Kazushi MATSUO , Toshihiko Matsuoka
发明人： Kazushi MATSUO , Toshihiko Matsuoka
IPC分类号： H04L7/00 , H04J3/24
CPC分类号： H04L12/403 , H04L7/046
摘要： A synchronization signal detection apparatus includes a temporary synchronization signal detector and a final synchronization signal detector. A header of a synchronization signal has at least M successive bits of a first level, where M is an integer more than the Nth power of 2, and N is a positive integer. The synchronization signal has alternating bits starting with a second level. The temporary synchronization signal detector detects the Nth power of 2 successive bits of the first level as a temporary synchronization signal when receiving the Nth power of 2 successive bits of the first level before receiving the alternating bits. The final synchronization signal detector determines that the detected temporary synchronization signal is the header when receiving the at least M successive bits of the first level.
摘要翻译：同步信号检测装置包括临时同步信号检测器和最终同步信号检测器。同步信号的标题具有至少M个第一级的连续位，其中M是大于第N次幂2的整数，N是正整数。同步信号具有以第二电平开始的交替位。临时同步信号检测器在接收到交替位之前接收到第一电平的2个连续位的第N个功率时，将第一电平的2个连续位的第N个功率作为临时同步信号进行检测。当接收到第一级的至少M个连续位时，最终同步信号检测器确定检测到的临时同步信号是标题。

4. 发明授权

US08504748B2 Communication slave and communication network system 有权
标题翻译：通信从站和通信网络系统
公开(公告)号：US08504748B2
公开(公告)日：2013-08-06
申请号：US12969641
申请日：2010-12-16
申请人： Kazushi Matsuo , Hideaki Ishihara , Toshihiko Matsuoka
发明人： Kazushi Matsuo , Hideaki Ishihara , Toshihiko Matsuoka
IPC分类号： G06F13/00
CPC分类号： H04L12/403 , H04L29/12254 , H04L61/2038
摘要： In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion.
摘要翻译：在其中主站和多个通信从站以菊花链方式通过高电位侧总线和低电位侧总线耦合的通信网络系统中，每个通信从站包括控制电路，电阻元件和电位差检测部分。控制电路控制与主机的通信。电阻元件在位于控制电路与高电位侧总线耦合的点的下游的部分插入高电位侧总线。电位差检测部检测电阻元件的上游端子与低电位侧总线之间的电位差。控制电路根据由电位差检测部检测出的电位差设定用于与主机通信的ID值。

5. 发明申请

US20110185093A1 COMMUNICATION SLAVE AND COMMUNICATION NETWORK SYSTEM 有权
标题翻译：通信从站和通信网络系统
公开(公告)号：US20110185093A1
公开(公告)日：2011-07-28
申请号：US12969641
申请日：2010-12-16
申请人： Kazushi MATSUO , Hideaki ISHIHARA , Toshihiko MATSUOKA
发明人： Kazushi MATSUO , Hideaki ISHIHARA , Toshihiko MATSUOKA
IPC分类号： G06F13/14
CPC分类号： H04L12/403 , H04L29/12254 , H04L61/2038
摘要： In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion.
摘要翻译：在其中主站和多个通信从站通过高电位侧总线和低电位侧总线以菊花链方式耦合的通信网络系统中，每个通信从站包括控制电路，电阻元件和电位差检测部分。控制电路控制与主机的通信。电阻元件在位于控制电路与高电位侧总线耦合的点的下游的部分插入高电位侧总线。电位差检测部检测电阻元件的上游端子与低电位侧总线之间的电位差。控制电路根据由电位差检测部检测出的电位差设定用于与主机通信的ID值。

6. 发明申请

US20090096504A1 Data reception apparatus and microcomputer having the same 有权
标题翻译：数据接收装置和具有该数据接收装置的微型计算机
公开(公告)号：US20090096504A1
公开(公告)日：2009-04-16
申请号：US12285581
申请日：2008-10-09
申请人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
发明人： Kazushi Matsuo , Toshihiko Matsuoka , Hideaki Ishihara
IPC分类号： H03K3/011
CPC分类号： H03L1/025 , H03L1/026 , H03L7/06
摘要： A data reception apparatus includes: an oscillation circuit that multiplies or divides an oscillation signal from a CR oscillator based on a cycle setting value, and outputs a clock signal corresponding to the multiplied or divided oscillation signal; a temperature detector; a memory; a clock cycle setting element that reads the cycle setting value corresponding to the temperature from the memory, and inputs the cycle setting value into the oscillation circuit; a receiver that receives a data signal defined by the clock signal; a measurement element that measures a unit bit length of the data signal by counting the clock signal; and a correction element that corrects the cycle setting value based on a count value of the clock signal and a reference count value of a reference cycle corresponding to the unit bit length, and rewrites the cycle setting value with the corrected cycle setting value.
摘要翻译：数据接收装置包括：振荡电路，其根据周期设定值对来自CR振荡器的振荡信号进行倍数或分频，并输出与所乘的或分频的振荡信号对应的时钟信号; 温度检测器; 记忆时钟周期设定元件，其从存储器读取与温度对应的周期设定值，并将该周期设定值输入到振荡电路中; 接收器，接收由时钟信号定义的数据信号; 测量元件，通过对时钟信号进行计数来测量数据信号的单位比特长度; 以及校正元件，其基于时钟信号的计数值和与单位比特长度对应的基准周期的基准计数值来校正周期设定值，并且以修正的周期设定值重写周期设定值。

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