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1. 发明授权

US5412615A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5412615A
公开(公告)日：1995-05-02
申请号：US166099
申请日：1993-12-14
申请人： Hiromi Noro , Shinnosuke Kamata , Yoshinori Okajima
发明人： Hiromi Noro , Shinnosuke Kamata , Yoshinori Okajima
IPC分类号： G06F9/38 , G11C7/22 , G11C11/407 , G11C11/413 , G11C11/417 , G11C8/00
CPC分类号： G11C7/225 , G11C7/22
摘要： This invention provides an apparatus in which a time difference between an eternal clock signal and an internal clock signal is eliminated, and in which a high operation speed even at a high operation frequency is accomplished without causing erroneous circuit operations. A semiconductor integrated circuit device is equipped with a signal generator for generating an internal clock signal for determining an operation timing of an internal circuit from an external clock signal. The semiconductor integrated circuit device includes a delay unit for bringing an edge of the external clock signal into conformity with the edge of the internal clock signal by delaying the output of the signal generator by the time obtained by subtracting a time corresponding to a circuit delay of the signal generator from a time corresponding to some integral multiple of a 1/2 cycle of the external clock signal.
摘要翻译：本发明提供一种其中消除了永恒时钟信号和内部时钟信号之间的时间差的装置，并且其中即使在高操作频率下也实现高运行速度而不引起错误的电路操作。半导体集成电路器件配备有信号发生器，用于产生用于从外部时钟信号确定内部电路的操作定时的内部时钟信号。半导体集成电路器件包括延迟单元，用于通过将信号发生器的输出延迟通过减去与电路延迟相对应的时间而获得的时间，使得外部时钟信号的边沿与内部时钟信号的边缘一致信号发生器从对应于外部时钟信号的1/2周期的一些整数倍的时间开始。

2. 发明授权

US5280456A Semiconductor memory device enabling change of output organization with high speed operation 失效
标题翻译：半导体存储器件能够实现高速运行时输出组织的改变
公开(公告)号：US5280456A
公开(公告)日：1994-01-18
申请号：US944953
申请日：1992-09-15
申请人： Yoshinori Okajima , Yoshihide Sato , Shinnosuke Kamata
发明人： Yoshinori Okajima , Yoshihide Sato , Shinnosuke Kamata
IPC分类号： G11C11/41 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/419
CPC分类号： G11C7/1006
摘要： A semiconductor memory device enabling change of the output organization has a plurality of memory cell array portions each having a plurality of memory cells for storing data, a plurality of data buses for transferring data, a plurality of sense amplifiers for sensing data of a selected memory cell of the memory cell array portions, and a plurality of output gates connected to the sense amplifiers. At least two of the sense amplifiers are connected to each of the memory cell array portions through the data buses, respectively. The selection of the sense amplifiers is controlled to be activated or deactivated by control signals, to thereby change the output organization. Therefore, a delay in data transmission can be eliminated, and a high speed operation can be realized.
摘要翻译：能够改变输出组织的半导体存储器件具有多个存储单元阵列部分，每个存储单元阵列部分具有用于存储数据的多个存储单元，用于传送数据的多个数据总线，用于感测所选存储器的数据的多个读出放大器存储单元阵列部分的单元，以及连接到读出放大器的多个输出门。至少两个感测放大器分别通过数据总线连接到每个存储单元阵列部分。读出放大器的选择由控制信号控制成激活或去激活，从而改变输出组织。因此，可以消除数据传输的延迟，并且可以实现高速操作。

3. 发明授权

US07941730B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07941730B2
公开(公告)日：2011-05-10
申请号：US11443031
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G06F11/10 , G06F13/14
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译：半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。因此，可以使用一种半导体存储器作为多种半导体存储器。这消除了开发多种半导体存储器的需要，降低了开发成本。

4. 发明授权

US07533196B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07533196B2
公开(公告)日：2009-05-12
申请号：US11589840
申请日：2006-10-31
申请人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
发明人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
IPC分类号： G06F13/28
CPC分类号： G06F12/0692 , G06F15/7857
摘要： A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
摘要翻译：半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。

5. 发明授权

US07428182B1 Electronic circuit system, and signal transmission method, to improve signal transmission efficiency and simplify signal transmission management 失效
标题翻译：电子电路系统和信号传输方式，提高信号传输效率，简化信号传输管理
公开(公告)号：US07428182B1
公开(公告)日：2008-09-23
申请号：US09372166
申请日：1999-08-11
申请人： Yoshinori Okajima
发明人： Yoshinori Okajima
IPC分类号： G11C8/00
CPC分类号： H04L12/42
摘要： An electronic circuit system has at least three macro circuits and a plurality of signal lines for connecting the macro circuits to one another into a loop. Each of the macro circuits includes a logic circuit and a memory circuit and has a plurality of input terminals and a plurality of output terminals. Signals are transmitted through the loop in a single specified direction in synchronization with a clock signal. Each of the macro circuits receives the signals at the input terminals thereof, accepts the signals if the signals are destined for the macro circuit, and transfers the signals to the output terminals thereof if the signals are not destined for the macro circuit. Even if the macro circuits simultaneously transmit signals, the electronic circuit system transmits the signals in the specified direction through the loop in synchronization with the clock signal up to destination macro circuits.
摘要翻译：电子电路系统具有至少三个宏电路和用于将宏电路彼此连接成环路的多条信号线。宏电路中的每一个包括逻辑电路和存储电路，并且具有多个输入端子和多个输出端子。信号与时钟信号同步地在单个指定方向上通过环路传输。每个宏电路在其输入端接收信号，如果信号指向宏电路，则接收信号，并且如果信号不是用于宏电路，则将信号传送到其输出端。即使宏电路同时发送信号，电子电路系统也可以与到目标宏电路的时钟信号同步地通过环路在指定方向上发送信号。

6. 发明授权

US07417884B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07417884B2
公开(公告)日：2008-08-26
申请号：US11443030
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C5/06 , H04B10/00
CPC分类号： G06F13/4243 , G11C5/066 , G11C7/1006
摘要： A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.
摘要翻译：存储器控制器将每个由多个位组成的访问信号复用为光信号并输出复用的光信号。此时，产生根据存储器件波长不同的光信号。存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。存储器接口单元不需要包括用于识别存储器件的解码电路。

7. 发明申请

US20070192527A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070192527A1
公开(公告)日：2007-08-16
申请号：US11443031
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译：半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。因此，可以使用一种半导体存储器作为多种半导体存储器。这消除了开发多种半导体存储器的需要，降低了开发成本。

8. 发明申请

US20070188210A1 Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof 失效
标题翻译：定时控制器和控制延迟电路，用于通过改变相位来控制信号的定时或延迟时间
公开(公告)号：US20070188210A1
公开(公告)日：2007-08-16
申请号：US11723602
申请日：2007-03-21
申请人： Yoshinori Okajima
发明人： Yoshinori Okajima
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K5/135 , H03K2005/00039 , H03L7/0812
摘要： A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.
摘要翻译：受控延迟电路具有第一栅极链和第二栅极链。第一栅极链用于测量第一控制信号的转换点和第二控制信号的转换点之间的时间差。接收在第一门链中产生并表示时间差的第三信号的第二门链用于根据时间差从输入到输出提供适当的延迟时间。受控延迟电路能够根据控制信号的周期适当地控制控制信号的定时。

9. 发明授权

US06384671B1 Electronic circuit apparatus for transmitting signals through a bus and semiconductor device for generating a predetermined stable voltage 有权
标题翻译：用于通过总线和半导体器件发送信号以产生预定稳定电压的电子电路装置
公开(公告)号：US06384671B1
公开(公告)日：2002-05-07
申请号：US09541699
申请日：2000-04-03
申请人： Masao Taguchi , Satoshi Eto , Yoshinori Okajima
发明人： Masao Taguchi , Satoshi Eto , Yoshinori Okajima
IPC分类号： G05F110
CPC分类号： H04L25/0278 , H03K17/16 , H04L25/028 , H04L25/0292 , H04L25/0298
摘要： An electronic circuit apparatus having a bus, a plurality of stubs branched from the bus, and a plurality of semiconductor devices having signal input/output terminals connected to the corresponding stubs. The electronic circuit apparatus includes at least one impedance circuit arranged between the bus and at least one of the stubs, and each impedance circuit has a high-pass filter characteristic. Therefore, ringing is suppressed, attenuation in the high-frequency components of a transmission signal is prevented, the definition of the signal is maintained, and transmission frequency and speed are both improved.
摘要翻译：具有总线，从总线分支的多个短截线的电子电路装置以及具有连接到对应短线的信号输入/输出端子的多个半导体器件。电子电路装置包括布置在总线和至少一个短截线之间的至少一个阻抗电路，并且每个阻抗电路具有高通滤波器特性。因此，抑制振铃，防止传输信号的高频分量的衰减，维持信号的定义，并且提高传输频率和速度。

10. 发明授权

US6114890A Skew-reduction circuit 失效
标题翻译：减速电路
公开(公告)号：US6114890A
公开(公告)日：2000-09-05
申请号：US967658
申请日：1997-11-10
申请人： Yoshinori Okajima , Tsuyoshi Higuchi
发明人： Yoshinori Okajima , Tsuyoshi Higuchi
IPC分类号： H03L7/081 , H03L7/087 , H03K5/12
CPC分类号： H03L7/0805 , H03L7/0814 , H03L7/087
摘要： A circuit includes a first phase-adjustment circuit adjusting phases of rising edges and falling edges of an original signal, and a phase-delay circuit receiving a phase-adjusted signal from said first phase-adjustment circuit and generating a delay signal by delaying said phase-adjusted signal by a predetermined phase amount. The circuit further includes a phase-comparison circuit comparing phases of edges between said phase-adjusted signal and said delay signal so as to control said first phase-adjustment circuit such that said phases of edges satisfy a predetermined phase relation.
摘要翻译：电路包括调整原始信号的上升沿和下降沿的相位的第一相位调整电路，以及从所述第一相位调整电路接收相位调整信号的相位延迟电路，并通过延迟所述相位产生延迟信号 - 调整信号预定相位量。电路还包括相位比较电路，比较所述相位调整信号和所述延迟信号之间的边沿的相位，以便控制所述第一相位调整电路，使得所述边缘相位满足预定的相位关系。

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