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1. 发明授权

US08502505B2 Battery driving device, load control method, integrated circuit and load control program 失效
标题翻译：电池驱动装置，负载控制方法，集成电路和负载控制程序
公开(公告)号：US08502505B2
公开(公告)日：2013-08-06
申请号：US12302559
申请日：2007-05-29
申请人： Hideyuki Kanzaki , Masayoshi Tojima
发明人： Hideyuki Kanzaki , Masayoshi Tojima
IPC分类号： H02J7/00
CPC分类号： H02J7/0029
摘要： A battery-driven device extends an operating time of a battery (a secondary battery). A battery control unit included in the battery drive-device stores therein one or more voltage thresholds, and detects a sharp voltage drop that occurs immediately after the start of discharging of a battery that is fully charged, based on the current and voltage of the battery and the stored voltage thresholds. Upon detecting a sharp voltage drop, the battery control unit decreases power consumption of the battery.
摘要翻译：电池驱动装置延长电池（二次电池）的工作时间。包括在电池驱动装置中的电池控制单元存储一个或多个电压阈值，并且基于电池的电流和电压来检测在完全充电的电池的放电开始之后立即发生的急剧的电压降和存储的电压阈值。当检测到急剧的电压降时，电池控制单元降低电池的功耗。

2. 发明授权

US08438523B2 Integrated circuit manufacturing method and semiconductor integrated circuit 有权
标题翻译：集成电路制造方法和半导体集成电路
公开(公告)号：US08438523B2
公开(公告)日：2013-05-07
申请号：US13383335
申请日：2011-05-27
申请人： Daisuke Iwahashi , Masayoshi Tojima , Tokuzo Kiyohara
发明人： Daisuke Iwahashi , Masayoshi Tojima , Tokuzo Kiyohara
IPC分类号： G06F17/50
CPC分类号： H01L27/0207
摘要： In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO block is determined, placement of the IO block is determined such that the IO block is placed close to the external terminal to alleviate constraints on the wiring between the IO block and the external terminal, and timing adjustment circuits whose number is determined according to the wiring length of a bus (or a shared bus) connecting a data transfer circuit and the IO block is inserted into the bus.
摘要翻译：在半导体集成电路制造方法的布局设计步骤中，当发现在外部端子与外部端子对应的IO块（外部端子I / F电路）之间的布线长度在包括功能块和IO块被确定，IO块的放置被确定为使得IO块靠近外部端子放置以减轻对IO块和外部端子之间的布线的约束，以及定时调整电路的数量是根据将数据传输电路和IO块连接的总线（或共享总线）的布线长度确定为总线。

3. 发明授权

US08081683B2 Decoding-processing apparatus for decoding bitstreams encoded in accordance with an arithmetic-encoding system in image compression and method for performing the same 有权
标题翻译：用于对图像压缩中的算术编码系统进行编码的比特流进行解码的解码处理装置及其执行方法
公开(公告)号：US08081683B2
公开(公告)日：2011-12-20
申请号：US12761507
申请日：2010-04-16
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译：一种使用中间格式解码比特流的解码处理装置。该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元（4）根据概率解码输入比特流，由此提供解码数据。该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值，检测单元（7）。

4. 发明申请

US20100232516A1 DECODING-PROCESSING APPARATUS AND METHOD 有权
标题翻译：解码处理设备和方法
公开(公告)号：US20100232516A1
公开(公告)日：2010-09-16
申请号：US12761507
申请日：2010-04-16
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/26
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译：一种使用中间格式解码比特流的解码处理装置。该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元（4）根据概率解码输入比特流，由此提供解码数据。该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值，检测单元（7）。

5. 发明申请

US20100232496A1 DECODING-PROCESSING APPARATUS AND METHOD 有权
公开(公告)号：US20100232496A1
公开(公告)日：2010-09-16
申请号：US12761493
申请日：2010-04-16
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/26
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).

6. 发明授权

US07599563B2 Data-transceiving equipment, image processor, and image-processing method 失效
标题翻译：数据收发设备，图像处理器和图像处理方法
公开(公告)号：US07599563B2
公开(公告)日：2009-10-06
申请号：US10541371
申请日：2003-12-22
申请人： Masashi Hoshino , Takashi Hashimoto , Masayoshi Tojima
发明人： Masashi Hoshino , Takashi Hashimoto , Masayoshi Tojima
IPC分类号： G06K9/36
CPC分类号： H04N7/147 , H04N5/445 , H04N5/44508 , H04N5/45 , H04N5/765 , H04N5/772 , H04N5/907 , H04N9/8042 , H04N9/8227 , H04N9/8233 , H04N21/42653 , H04N21/4334 , H04N21/8146
摘要： An encoding unit (44) individually encodes display image-forming image data, i.e., image data from an image input unit (2), decoded data from a decoding unit (46), and graphics image data from a graphics-generating unit (47). A storing unit (45) stores the individually encoded image data. As a result, when a user intends to reuse, more specifically, replay, edit, or transmit the stored display image, the user can selectively decode required image elements, thereby reusing the selectively decoded image elements. This feature provides improved user-friendliness.
摘要翻译：编码单元（44）对来自图像输入单元（2）的图像数据，来自解码单元（46）的解码数据和来自图形生成单元（47）的图形图像数据的显示图像形成图像数据分别进行编码）。存储单元（45）存储单独编码的图像数据。结果，当用户打算重用，更具体地，重放，编辑或发送所存储的显示图像时，用户可以选择性地解码所需的图像元素，从而重新使用选择性地解码的图像元素。此功能提供更好的用户友好性。

7. 发明授权

US07533196B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07533196B2
公开(公告)日：2009-05-12
申请号：US11589840
申请日：2006-10-31
申请人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
发明人： Masayoshi Tojima , Hiroshi Miyajima , Yoshinori Okajima
IPC分类号： G06F13/28
CPC分类号： G06F12/0692 , G06F15/7857
摘要： A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.
摘要翻译：半导体集成电路装置包括多个内部存储器，构成具有编解码功能的第一处理单元的主处理器，以及构成用于视频显示处理的第二处理单元的视频接口和图形处理器。半导体集成电路器件在连接到作为外部处理单元的CPU和外部存储器时工作。半导体集成电路装置具有存储器配置控制器，用于根据应用控制对第一，第二和外部处理单元的存储器分配。

8. 发明授权

US06731293B2 Image output device and image output control method 失效
标题翻译：图像输出设备和图像输出控制方式
公开(公告)号：US06731293B2
公开(公告)日：2004-05-04
申请号：US09867708
申请日：2001-05-31
申请人： Masayoshi Tojima , Toshihiro Moriiwa , Masatoshi Matsuo
发明人： Masayoshi Tojima , Toshihiro Moriiwa , Masatoshi Matsuo
IPC分类号： G06F1300
CPC分类号： G09G5/393 , G09G5/18 , G09G5/397 , G09G2340/0407
摘要： The present invention provides an image output device which can periodically update display of image data as well as update the display images immediately and with minimum data transfer. A data transfer request control circuit 107 including a frame rate register 108 for deciding a data transfer request issue cycle and a data transfer request issuing unit 109 is provided in a video processing unit 104 of the image output device. When an update flag is set in the frame rate register 108, the data transfer request is issued in the next transfer section, regardless of the periodic transfer cycle, and the image data stored in the frame memory 106 are update.
摘要翻译：本发明提供一种可以周期性地更新图像数据的显示以及立即更新显示图像并且以最小的数据传送的图像输出装置。包括用于决定数据传送请求发布周期的帧速率寄存器108和数据传送请求发布单元109的数据传送请求控制电路107被提供在图像输出设备的视频处理单元104中。当在帧速率寄存器108中设置更新标志时，无论周期性传送周期如何，都在下一个传送部分中发出数据传送请求，并且更新存储在帧存储器106中的图像数据。

9. 发明授权

US07843487B2 System of linkable cameras, each receiving, contributing to the encoding of, and transmitting an image 有权
标题翻译：可连接摄像机的系统，每个接收，有助于编码和发送图像
公开(公告)号：US07843487B2
公开(公告)日：2010-11-30
申请号：US11892852
申请日：2007-08-28
申请人： Masayoshi Tojima
发明人： Masayoshi Tojima
IPC分类号： H04N7/00 , H04N13/00 , H04N13/02 , H04N5/228 , H04N5/76 , A61B1/04 , G03B35/00 , G06F3/00
CPC分类号： H04N5/232 , H04N5/23238 , H04N5/23245
摘要： The camera system of the present invention includes a plurality of cameras each including an imaging unit and an image processing unit. If configured to operate in a mode that is for cooperation with other cameras, a first camera included in the camera system causes the image processing unit thereof to receive images from other cameras, and generate synthesized image by synthesizing the received images and an image captured by the imaging unit thereof. The first camera transmits the generated synthesized image to a second camera included in the camera system. The second camera causes, if configured to operate in the mode that is for cooperation with other cameras, the image processing unit thereof to perform part or whole of encoding of the received synthesized image.
摘要翻译：本发明的照相机系统包括多个摄像机，每个照相机包括成像单元和图像处理单元。如果被配置为以与其他相机协作的模式操作，则包括在相机系统中的第一相机使其图像处理单元从其他相机接收图像，并且通过合成所接收的图像和由其成像单元。第一相机将生成的合成图像发送到相机系统中包括的第二相机。第二相机如果配置为以与其他相机协作的模式操作，则其图像处理单元执行接收到的合成图像的部分或全部编码。

10. 发明授权

US07724830B2 Decoding-processing apparatus and method 有权
标题翻译：解码处理装置和方法
公开(公告)号：US07724830B2
公开(公告)日：2010-05-25
申请号：US11665063
申请日：2005-11-02
申请人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
发明人： Masayoshi Tojima , Masayasu Iguchi , Kiyofumi Abe , Hiroaki Toida , Takahiro Nishi
IPC分类号： H04N7/32
CPC分类号： H04N19/00006 , H03M7/4006 , H04N19/10 , H04N19/40 , H04N19/70 , H04N19/89 , H04N19/91
摘要： A decoding-processing apparatus that decodes bitstreams using an intermediate format. The apparatus includes a context-calculating unit (2) calculating the probability of symbols contained in incoming bitstreams, a parameter-generating unit (3) generating parameters for use in the context-calculating unit (2), and an arithmetic decoding-calculating unit (4) decoding the incoming bitstreams in accordance with the probability, thereby providing decoded data. The apparatus also includes a stream-converting unit (5) converting the decoded data into intermediate bitstreams, a storage unit (6) storing the intermediate bitstreams, a synchronization-detecting unit (7) detecting calculation start timing from the intermediate bitstreams fed out of the storage unit (6), thereby providing detected calculation start timing, and a multivalued calculating unit (8) permitting the intermediate bitstreams fed out of the storage unit (6) to be multivalued in synchronism with the detected calculation start timing from the synchronization-detecting unit (7).
摘要翻译：一种使用中间格式解码比特流的解码处理装置。该装置包括：计算输入比特流中包含的符号概率的上下文计算单元（2），生成上下文计算单元（2）中使用的参数的参数生成单元（3）和算术解码计算单元（4）根据概率解码输入比特流，由此提供解码数据。该装置还包括将解码数据转换为中间比特流的流转换单元（5），存储中间比特流的存储单元（6），同步检测单元（7）从从存储单元（6），从而提供检测到的计算开始定时;以及多值计算单元（8），其允许从存储单元（6）馈送的中间比特流与来自同步的计算开始定时的检测到的计算开始定时同步多值，检测单元（7）。

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