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1. 发明申请

US20110215435A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110215435A1
公开(公告)日：2011-09-08
申请号：US13038349
申请日：2011-03-01
申请人： Hiroki WAKIMOTO , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
发明人： Hiroki WAKIMOTO , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
IPC分类号： H01L29/06 , H01L21/78 , H01L21/302
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
摘要翻译：本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。提供p型区域并且电连接到p +型隔离层。提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

2. 发明授权

US08604584B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08604584B2
公开(公告)日：2013-12-10
申请号：US13038349
申请日：2011-03-01
申请人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
发明人： Hiroki Wakimoto , Kenichi Iguchi , Koh Yoshikawa , Tsunehiro Nakajima , Shunsuke Tanaka , Masaaki Ogino
IPC分类号： H01L21/78 , H01L21/302
CPC分类号： H01L21/308 , H01L21/302 , H01L21/78 , H01L29/06
摘要： Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
摘要翻译：本发明的一些实施例涉及能够防止电特性劣化的半导体器件和半导体器件的制造方法。 p型集电极区域设置在n型漂移区域的背面的表面层上。在元件的末端提供了用于获得反向阻挡能力的p +型隔离层。此外，设置从n型漂移区的背面向p +型隔离层延伸的凹部。提供p型区域并且电连接到p +型隔离层。提供p +型隔离层，以便包括具有作为一侧的凹部的底部和侧壁之间的边界的解理面。

3. 发明申请

US20070252195A1 VERTICAL AND TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE 有权
标题翻译：垂直和倾斜型绝缘栅MOS半导体器件
公开(公告)号：US20070252195A1
公开(公告)日：2007-11-01
申请号：US11741015
申请日：2007-04-27
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L31/00
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n + + +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

4. 发明授权

US07737490B2 Vertical and trench type insulated gate MOS semiconductor device 有权
标题翻译：垂直和沟槽型绝缘栅MOS半导体器件
公开(公告)号：US07737490B2
公开(公告)日：2010-06-15
申请号：US11741015
申请日：2007-04-27
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

5. 发明授权

US08242556B2 Vertical and trench type insulated gate MOS semiconductor device 有权
标题翻译：垂直和沟槽型绝缘栅MOS半导体器件
公开(公告)号：US08242556B2
公开(公告)日：2012-08-14
申请号：US12767356
申请日：2010-04-26
申请人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
发明人： Koh Yoshikawa , Hiroki Wakimoto , Masahito Otsuki
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.
摘要翻译：提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。这使得器件能够实现低导通电阻和增强的关断能力。

6. 发明授权

US08278682B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08278682B2
公开(公告)日：2012-10-02
申请号：US13116650
申请日：2011-05-26
申请人： Koh Yoshikawa , Kenichi Iguchi
发明人： Koh Yoshikawa , Kenichi Iguchi
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404
摘要： A semiconductor device that has a reduced size and exhibits a superior blocking voltage capability. A semiconductor device includes an edge termination structure between an active region and an isolation region, the edge termination structure being composed of an edge termination structure for a forward bias section and an edge termination structure for a reverse bias section. A plurality of field limiting rings (FLRs) and a plurality of field plates (FPs) are provided in the edge termination structure for the forward bias section and the edge termination structure for the reverse bias section. A first forward FP that is the nearest of the plurality of FPs to the edge termination structure for the reverse bias section is formed to extend towards the isolation region side. A first reverse FP that is the nearest of the plurality of FPs to the edge termination structure for the forward bias section is formed to extend towards the active region side. The first reverse FP stops the depletion layer expanding from the active region on application of a forward voltage. The first forward FP stops the depletion layer expanding from the isolation region on application of a reverse voltage.
摘要翻译：具有减小的尺寸并且具有优异的阻挡电压能力的半导体器件。半导体器件包括在有源区和隔离区之间的边缘终端结构，边缘终端结构由用于正偏压部分的边缘终端结构和用于反向偏压部分的边缘终端结构组成。在用于正偏压部分的边缘终端结构和用于反向偏压部分的边缘终端结构中，设置有多个场限制环（FLR）和多个场板（FP）。形成朝向隔离区域侧延伸到与反向偏置部分的边缘终端结构相邻的多个FP中的最近的第一前向FP。形成朝向偏置部分的边缘终端结构的多个FP中最接近的第一反向FP朝向有源区域侧延伸。第一反向FP在施加正向电压时停止从有源区扩展的耗尽层。第一个前向FP在施加反向电压时停止从隔离区扩展的耗尽层。

7. 发明授权

US09466711B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09466711B2
公开(公告)日：2016-10-11
申请号：US12865330
申请日：2009-01-28
申请人： Seiji Momota , Hitoshi Abe , Takashi Shiigi , Takeshi Fujii , Koh Yoshikawa , Tetsutaro Imagawa , Masaki Koyama , Makoto Asai
发明人： Seiji Momota , Hitoshi Abe , Takashi Shiigi , Takeshi Fujii , Koh Yoshikawa , Tetsutaro Imagawa , Masaki Koyama , Makoto Asai
IPC分类号： H01L29/78 , H01L29/96 , H01L29/739 , H01L29/08 , H01L29/10 , H01L29/423
CPC分类号： H01L27/0629 , H01L27/0658 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/7395 , H01L29/7397 , H01L29/7815 , H01L29/7827
摘要： Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).
摘要翻译：在主装置（24）的源电极（25）和电流检测装置（21）的电流检测电极（22）之间连接用于检测电流的电阻器。栅极绝缘体（36）的介电耐受电压大于电阻器和流过电流检测装置（21）的反向偏压的最大电流的乘积。主装置（24）的p体区域（32）的扩散长度短于电流检测装置（21）的p体（31）的扩散长度。主装置（24）的p体区域（32）的端部的曲率半径比电流检测装置（21）的p体（31）的曲率半径小。结果，在逆偏压下，主装置（24）的p体区域（32）的端部的电场变得比电流检测装置的p体区域（31）的电场强 21）。因此，主装置24中的雪崩击穿比电流检测装置（21）更容易发生。

8. 发明授权

US08334581B2 Semiconductor device exhibiting withstand voltages in the forward and reverse directions 有权
标题翻译：在正向和反向方向表现出耐受电压的半导体器件
公开(公告)号：US08334581B2
公开(公告)日：2012-12-18
申请号：US12975650
申请日：2010-12-22
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/404
摘要： A semiconductor device according to embodiments of the invention includes an n−-type drift region; a p-type base region formed selectively in the surface portion of the drift region; an n+-type emitter region and a p+-type body region, both formed selectively in the surface portion of base region; and an n-type shell region between the drift region and the base region, a shell region surrounding the entire region below base region. The shell region is doped more heavily than the drift region. The shell region contains an n-type impurity at an effective impurity amount of 8.0×1011 cm −2 or smaller. A drift region exhibits a resistivity low enough to prevent the depletion layer expanding from collector region, formed on the back surface of the drift region, toward a shell region from reaching the shell region.
摘要翻译：根据本发明的实施例的半导体器件包括n型漂移区; 选择性地形成在漂移区域的表面部分中的p型基极区域; n +型发射极区域和p +型体区域，均选择性地形成在基极区域的表面部分中; 以及漂移区域和基极区域之间的n型壳体区域，围绕在基底区域下方的整个区域的壳体区域。壳体区域比漂移区域更重掺杂。外壳区域包含有效杂质量为8.0×10 11 cm -2以下的n型杂质。漂移区域具有足够低的电阻率，以防止耗尽层从形成在漂移区域的背面上的集电极区域朝向壳体区域到达壳体区域扩展。

9. 发明申请

US20110220962A1 SEMICONDUCTOR DEVICE HAVING INSULATED GATE SEMICONDUCTOR ELEMENT, AND INSULATED GATE BIPOLAR TRANSISTOR 有权
标题翻译：具有绝缘栅半导体元件和绝缘栅双极晶体管的半导体器件
公开(公告)号：US20110220962A1
公开(公告)日：2011-09-15
申请号：US13115137
申请日：2011-05-25
申请人： Masaki Koyama , Yoshifumi Okabe , Makoto Asai , Takeshi Fujii , Koh Yoshikawa
发明人： Masaki Koyama , Yoshifumi Okabe , Makoto Asai , Takeshi Fujii , Koh Yoshikawa
IPC分类号： H01L29/739
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4238 , H01L29/66348 , H01L29/7397
摘要： A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.
摘要翻译：具有IGBT的半导体器件包括：基板; 衬底上的漂移层和基底层; 穿过基层的沟槽将基层分成基部; 一个基部的发射极区域; 沟槽中的栅极元件; 发射极; 和集电极。一个基座部分提供通道层，而另一个基座部件提供没有发射极区域的浮动层。栅极元件包括靠近沟道层的栅极电极和与浮置层相邻的伪栅极电极。浮子层包括与沟道层相邻的第一浮动层和与沟道层分开的第二浮体层。虚拟栅电极和第一浮动层与基层上的第一浮动布线耦合。虚拟栅电极与第二浮动层隔离。

10. 发明授权

US07943991B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07943991B2
公开(公告)日：2011-05-17
申请号：US11614515
申请日：2006-12-21
申请人： Koh Yoshikawa
发明人： Koh Yoshikawa
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0865 , H01L29/1095 , H01L29/4236 , H01L29/66734
摘要： A semiconductor device is discloses that includes an n-type semiconductor substrate; an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately; p-type channel regions on the alternating conductivity type layer; and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions. The bottom of each trench is over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof.
摘要翻译：公开了一种半导体器件，其包括n型半导体衬底; 在半导体衬底上的交替导电型层，交替导电型层包括交替布置的n型漂移区和p型隔离区; 交替导电型层上的p型沟道区; 以及从p型沟道区的表面形成到各个n型漂移区的沟槽。每个沟槽的底部在p型分隔区域和n型漂移区域之间的pn结上方。半导体器件有助于防止导通电阻增加，获得更高的击穿电压，并减少其特性引起的变化。

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