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1. 发明授权

US07462911B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US07462911B2
公开(公告)日：2008-12-09
申请号：US11561652
申请日：2006-11-20
申请人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
发明人： Hiroki Wakimoto , Seiji Momota , Masahito Otsuki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0696 , H01L29/7397
摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.
摘要翻译：公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。它包括通过沟槽分成不同p型基极区的p型基极层。仅在一些p型基区中形成N型源极区。在沟槽IGBT的有源区域中有一个栅极流道。形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关，由式25 <= {N1 /（N1 + N2）}×100 <= 75。

2. 发明申请

US20070075331A1 INSULATED GATE SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20070075331A1
公开(公告)日：2007-04-05
申请号：US11561652
申请日：2006-11-20
申请人： Hiroki WAKIMOTO , Seiji MOMOTA , Masahito OTSUKI
发明人： Hiroki WAKIMOTO , Seiji MOMOTA , Masahito OTSUKI
IPC分类号： H01L29/74
CPC分类号： H01L29/0696 , H01L29/7397
摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.
摘要翻译：公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。它包括通过沟槽分成不同p型基极区的p型基极层。仅在一些p型基区中形成N型源极区。在沟槽IGBT的有源区域中有一个栅极流道。形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关，由式25 <= {N1 /（N1 + N2x100 <= 75。

3. 发明授权

US06737705B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06737705B2
公开(公告)日：2004-05-18
申请号：US09843251
申请日：2001-04-26
申请人： Seiji Momota , Yuichi Onozawa , Masahito Otsuki , Hiroki Wakimoto
发明人： Seiji Momota , Yuichi Onozawa , Masahito Otsuki , Hiroki Wakimoto
IPC分类号： H01L29745
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/407
摘要： A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate. The ratio of the width of the first regions to the width of the second regions of p-type base layer is from 1:2 to 1:7. The device facilitates in reducing the total losses by reducing the switching loss while suppressing the on-voltage thereof as low as the on-voltage of the IEGT.
摘要翻译：沟槽型IGBT包括硅衬底，硅衬底上的轻掺杂n型漂移层和n型漂移层上的p型基极层。 p型基极层比n型漂移层掺杂更多，由第一区域和第二区域形成。在p型基底层的第一区域的表面部分中选择性地形成N +型源极区域。沟槽从n +型源区的表面通过p型基底层向下到达n型漂移层。栅极氧化膜覆盖每个沟槽的内表面。栅极设置在沟槽中，其中栅电极经由相应的栅氧化膜面对p型基极层。发射极电极与p型基极层和n +型源极区域的第一区域直接接触。集电极设置在硅衬底的背面上。第一区域的宽度与p型基底层的第二区域的宽度的比例为1:2至1:7。该器件通过降低开关损耗同时将其导通电压抑制得低至IEGT的导通电压，从而有助于降低总损耗。

4. 发明授权

US08309409B2 Method for fabricating trench gate to prevent on voltage parasetic influences 有权
标题翻译：制造沟槽栅极以防止电压寄生影响的方法
公开(公告)号：US08309409B2
公开(公告)日：2012-11-13
申请号：US13027761
申请日：2011-02-15
申请人： Seiji Momota
发明人： Seiji Momota
IPC分类号： H01L21/338 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0856 , H01L29/66727 , H01L29/66734
摘要： A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.
摘要翻译：半导体器件制造方法包括在第一导电性的第一半导体区域的表面层上形成具有高于第一半导体区域的杂质浓度的第二半导体区域的第二导电性区域; 形成穿过所述第二半导体区域的沟槽到所述第一半导体区域; 在第二半导体区域的表面以下的高度处经由绝缘膜将第一电极嵌入沟槽内; 在所述沟槽内形成层间绝缘膜，覆盖所述第一电极; 仅在第一电极的表面上留下层间绝缘膜; 去除所述第二半导体区域使得其表面定位成低于所述第一电极和所述层间绝缘膜之间的界面; 以及通过沟槽中的绝缘膜形成与第二半导体区域接触并与第一电极相邻的第二电极。

5. 发明申请

US20110207296A1 FABRICATION METHOD FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20110207296A1
公开(公告)日：2011-08-25
申请号：US13027761
申请日：2011-02-15
申请人： Seiji Momota
发明人： Seiji Momota
IPC分类号： H01L21/36
CPC分类号： H01L29/7813 , H01L29/0856 , H01L29/66727 , H01L29/66734
摘要： A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.
摘要翻译：半导体器件制造方法包括在第一导电性的第一半导体区域的表面层上形成具有高于第一半导体区域的杂质浓度的第二半导体区域的第二导电性区域; 形成穿过所述第二半导体区域的沟槽到所述第一半导体区域; 在第二半导体区域的表面以下的高度，经由绝缘膜将第一电极嵌入沟槽内; 在所述沟槽内形成层间绝缘膜，覆盖所述第一电极; 仅在第一电极的表面上留下层间绝缘膜; 去除所述第二半导体区域使得其表面定位成低于所述第一电极和所述层间绝缘膜之间的界面; 以及通过沟槽中的绝缘膜形成与第二半导体区域接触并与第一电极相邻的第二电极。

6. 发明申请

US20110012195A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110012195A1
公开(公告)日：2011-01-20
申请号：US12865330
申请日：2009-01-28
申请人： Seiji Momota , Hitoshi Abe , Takashi Shiigi , Takeshi Fujii , Koh Yoshikawa , Tetsutaro Imagawa , Masaki Koyama , Makoto Asai
发明人： Seiji Momota , Hitoshi Abe , Takashi Shiigi , Takeshi Fujii , Koh Yoshikawa , Tetsutaro Imagawa , Masaki Koyama , Makoto Asai
IPC分类号： H01L27/11
CPC分类号： H01L27/0629 , H01L27/0658 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/7395 , H01L29/7397 , H01L29/7815 , H01L29/7827
摘要： Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).
摘要翻译：在主装置（24）的源电极（25）和电流检测装置（21）的电流检测电极（22）之间连接用于检测电流的电阻器。栅极绝缘体（36）的介电耐受电压大于电阻器和流过电流检测装置（21）的反向偏压的最大电流的乘积。主装置（24）的p体区域（32）的扩散长度短于电流检测装置（21）的p体（31）的扩散长度。主装置（24）的p体区域（32）的端部的曲率半径比电流检测装置（21）的p体（31）的曲率半径小。结果，在逆偏压下，主装置（24）的p体区域（32）的端部的电场变得比电流检测装置的p体区域（31）的电场强 21）。因此，主装置24中的雪崩击穿比电流检测装置（21）更容易发生。

7. 发明申请

US20050158979A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050158979A1
公开(公告)日：2005-07-21
申请号：US10864917
申请日：2004-06-09
申请人： Seiji Momota , Eiji Mochizuki
发明人： Seiji Momota , Eiji Mochizuki
IPC分类号： H01L21/288 , H01L21/3205 , H01L21/329 , H01L23/52 , H01L29/06 , H01L29/417 , H01L29/861 , H01L21/76 , H01L21/44
CPC分类号： H01L29/66136 , H01L29/417 , H01L29/861 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： A method of manufacturing a semiconductor device is disclosed in which a metallic deposit is stably formed on the anode side with small variation in film thickness, and plating is prevented on the cathode side without carrying out any additional processing on the cathode side. The processed anode side causes no interference in subsequent processing. Insulator films are used to cover a scribe line, as well as a field plate or an open electrode provided on a surface of a silicon substrate before Ni electroless plating of an aluminum electrode is performed to form a metallic deposit on the electrode.
摘要翻译：公开了一种制造半导体器件的方法，其中在阳极侧稳定地形成金属沉积物，薄膜的厚度变化小，并且在阴极侧不会对阴极侧进行任何额外的处理来防止电镀。经处理的阳极侧在后续处理中不产生干扰。在进行铝电极的Ni化学镀以在电极上形成金属沉积物之前，使用绝缘膜覆盖划线，以及设置在硅衬底的表面上的场板或开放电极。

8. 发明授权

US08253222B2 Semiconductor device and fabrication method of semiconductor device 有权
标题翻译：半导体器件的半导体器件及其制造方法
公开(公告)号：US08253222B2
公开(公告)日：2012-08-28
申请号：US13027792
申请日：2011-02-15
申请人： Seiji Momota , Takeshi Fujii , Satoshi Kamijima , Makoto Asai
发明人： Seiji Momota , Takeshi Fujii , Satoshi Kamijima , Makoto Asai
IPC分类号： H01L29/41
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.
摘要翻译：半导体器件包括第一导电类型的第一半导体区域; 第二导电类型的第二半导体区域，设置在第一半导体区域的表面上，杂质浓度高于第一半导体区域; 穿过第二半导体区域到达第一半导体区域的沟槽; 经由绝缘膜设置在所述沟槽内的第一电极; 在所述第二半导体区域的表面层中设置为比所述第一电极的上端深的第一凹部，以与所述沟槽接触; 以及嵌入在第一凹部中的第二电极。

9. 发明授权

US08198697B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08198697B2
公开(公告)日：2012-06-12
申请号：US12816487
申请日：2010-06-16
申请人： Seiji Momota , Hitoshi Abe , Takeshi Fujii
发明人： Seiji Momota , Hitoshi Abe , Takeshi Fujii
IPC分类号： H01L31/058
CPC分类号： H01L29/7395 , H01L29/0696 , H01L29/7397 , H01L29/866
摘要： An IGBT is disclosed which separated into two groups (first and second IGBT portions). First and second Zener diodes each composed of series-connected Zener diode parts are disposed so as to correspond to the groups respectively. Each of the first and second Zener diodes has an anode side connected to a corresponding one of first and second polysilicon gate wirings, and a cathode side connected to an emitter electrode. Temperature dependence of a forward voltage drop of each of first and second Zener diodes is used for reducing a gate voltage of a group rising in temperature to throttle a current flowing in the group and reduce the temperature of the group to thereby attain equalization of the temperature distribution in a surface of a chip. In this manner, it is possible to provide an MOS type semiconductor device in which equalization of the temperature distribution in a surface of a chip or among chips can be attained.
摘要翻译：公开了分为两组（第一和第二IGBT部分）的IGBT。分别由串联连接的齐纳二极管部件构成的第一和第二齐纳二极管分别对应于组。第一和第二齐纳二极管中的每一个具有连接到第一和第二多晶硅栅极布线中的相应一个的阳极侧，以及连接到发射极的阴极侧。使用第一和第二齐纳二极管每个的正向压降的温度依赖性来降低温度上升的组的栅极电压，以节流在该组中流动的电流并降低该组的温度从而达到温度的均衡分布在芯片的表面。以这种方式，可以提供一种其中可以获得芯片表面或芯片之间的温度分布的均衡的MOS型半导体器件。

10. 发明申请

US20110204485A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20110204485A1
公开(公告)日：2011-08-25
申请号：US13027792
申请日：2011-02-15
申请人： Seiji Momota , Takeshi Fujii , Satoshi Kamijima , Makoto Asai
发明人： Seiji Momota , Takeshi Fujii , Satoshi Kamijima , Makoto Asai
IPC分类号： H01L29/41 , H01L21/76
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A semiconductor device includes a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on a surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; a trench that penetrates the second semiconductor region to reach the first semiconductor region; a first electrode disposed inside the trench via an insulating film; a first recess portion disposed deeper than an upper end of the first electrode, in a surface layer of the second semiconductor region, so as to be in contact with the trench; and a second electrode embedded in the first recess portion.
摘要翻译：半导体器件包括第一导电类型的第一半导体区域; 第二导电类型的第二半导体区域，设置在第一半导体区域的表面上，杂质浓度高于第一半导体区域; 穿过第二半导体区域到达第一半导体区域的沟槽; 经由绝缘膜设置在所述沟槽内的第一电极; 在所述第二半导体区域的表面层中设置为比所述第一电极的上端深的第一凹部，以与所述沟槽接触; 以及嵌入在第一凹部中的第二电极。

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