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1. 发明授权

US06799219B1 Method and apparatus for avoiding starvation in computer network 有权
标题翻译：避免计算机网络中的饥饿的方法和装置
公开(公告)号：US06799219B1
公开(公告)日：2004-09-28
申请号：US09653154
申请日：2000-08-31
申请人： Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie , Jeffrey D. Larson
发明人： Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie , Jeffrey D. Larson
IPC分类号： G06F1516
CPC分类号： H04L47/15 , H04L47/70 , H04L47/745 , H04L47/821 , H04L47/826
摘要： A method and apparatus for avoiding starvation at an initiator node in a computer network to which are connected at least one target node which provides service and a plurality of initiator nodes which request service from the target node. The method includes: when a request is received from the initiator node during a period that the target node is unable to provide service, returning a reject reply by attaching thereto reject time information that matches the period; when the target node is in a state capable of providing service, preferentially accepting a retry request carrying older reject time information; and when the target node is in the state capable of providing service, returning a reject reply by attaching thereto new reject time information in response to any first request received before retry requests arising from previously rejected requests are all accepted.
摘要翻译：一种用于避免在计算机网络中的发起者节点处的饥饿的方法和装置，至少一个提供服务的目标节点和从目标节点请求服务的多个发起方节点连接到该节点。该方法包括：当在目标节点不能提供服务的时段期间从发起者节点接收到请求时，通过附加拒绝回复的拒绝时间信息返回拒绝回复; 当目标节点处于能够提供服务的状态时，优先地接收携带较早拒绝时间信息的重试请求; 并且当目标节点处于能够提供服务的状态时，响应于在先前拒绝的请求引起的重试请求之前接收到的任何第一请求全部被接受，通过附加到新的拒绝时间信息来返回拒绝答复。

2. 发明授权

US06901451B1 PCI bridge over network 失效
标题翻译： PCI桥接网络
公开(公告)号：US06901451B1
公开(公告)日：2005-05-31
申请号：US09703477
申请日：2000-10-31
申请人： Takashi Miyoshi , Jeffrey D. Larson , Hirohide Sugahara , Takeshi Horie
发明人： Takashi Miyoshi , Jeffrey D. Larson , Hirohide Sugahara , Takeshi Horie
IPC分类号： G06F13/36 , G06F13/40 , G06F15/16 , H04L12/40
CPC分类号： G06F13/4027
摘要： One embodiment of the present invention provides a method for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a method for communicating request packet information from a network to a PCI environment. Another embodiment of the present invention provides a system for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a system for communicating request packet information from a network to a PCI environment.
摘要翻译：本发明的一个实施例提供了一种用于通过网络从PCI环境传送交易请求信息的方法。本发明的另一实施例提供了一种用于将请求分组信息从网络传送到PCI环境的方法。本发明的另一实施例提供一种用于通过网络从PCI环境传送交易请求信息的系统。本发明的另一个实施例提供一种用于将请求分组信息从网络传送到PCI环境的系统。

3. 发明授权

US06684281B1 Fast delivery of interrupt message over network 有权
标题翻译：通过网络快速传递中断消息
公开(公告)号：US06684281B1
公开(公告)日：2004-01-27
申请号：US09705451
申请日：2000-11-02
申请人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
发明人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt message to a second processor coupled to the computer network, by directly writing the interrupt message to a doorbell address range associated with the second processor in the PCI memory space of a first PCI bus to which the first processor is coupled. The doorbell address range is mapped to a doorbell space in the PCI memory space of a second PCI bus to which the second processor is coupled. The first PCI bus is coupled to the computer network through a first PCI network adaptor, which processes the write transaction and send it to the network. The second PCI bus is coupled to the computer network through a second PCI network adaptor, which receives the write transaction from the network and transforms the write transaction into an interrupt message to the second processor.
摘要翻译：计算机网络系统和用于通过计算机网络快速传递中断消息的方法使得耦合到计算机网络的第一处理器能够通过直接写入中断消息来非常快速地向耦合到计算机网络的第二处理器发送中断消息涉及与第一处理器耦合到的第一PCI总线的PCI存储器空间中与第二处理器相关联的门铃地址范围。门铃地址范围被映射到与第二处理器耦合到的第二PCI总线的PCI存储器空间中的门铃空间。第一个PCI总线通过第一个PCI网络适配器耦合到计算机网络，该PCI网络适配器处理写入事务并将其发送到网络。第二PCI总线通过第二PCI网络适配器耦合到计算机网络，第二PCI网络适配器从网络接收写入事务，并将写入事务转换为中断消息给第二处理器。

4. 发明授权

US06678758B2 Dynamic queuing for read/write requests 有权
标题翻译：动态排队读/写请求
公开(公告)号：US06678758B2
公开(公告)日：2004-01-13
申请号：US09778649
申请日：2001-02-05
申请人： Jeffrey D. Larson , Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie
发明人： Jeffrey D. Larson , Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F1314
CPC分类号： G06F13/387
摘要： A PCI (peripheral component interconnect) network adaptor manages read/write requests through the establishment of dynamic queues. The PCI network adaptor establishes a unique queue for each destination node that enables the requests for each node to be processed separately. The PCI network adaptor determines whether a remote read/write request should be added to the linked list for the destination node of the request or whether the request should be rejected. If the number of pending requests for the destination node is below a predetermined threshold and the entire buffer is not full, then the request is added to the linked list for the destination node. Otherwise, the request is rejected. For write requests, if the request is added to the linked list for the destination node, then any pending read requests for that node are aborted.
摘要翻译： PCI（外围组件互连）网络适配器通过建立动态队列来管理读/写请求。 PCI网络适配器为每个目标节点建立一个唯一的队列，使每个节点的请求能够单独处理。 PCI网络适配器确定是否应将远程读/写请求添加到请求的目标节点的链接列表中，还是请求被拒绝。如果目的地节点的未决请求数量低于预定阈值并且整个缓冲器未满，则将该请求添加到目的地节点的链表。否则，请求被拒绝。对于写入请求，如果将请求添加到目标节点的链接列表，则该节点的任何未决读取请求将被中止。

5. 发明授权

US06877039B2 Simplified pipeline writes over a network 有权
标题翻译：简化的流水线通过网络写入
公开(公告)号：US06877039B2
公开(公告)日：2005-04-05
申请号：US09842481
申请日：2001-04-25
申请人： Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie , Hirohide Sugahara
发明人： Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie , Hirohide Sugahara
IPC分类号： H04L12/40 , H04L12/28 , H04L29/06 , H04L29/08 , G06F15/16 , G06F13/36 , G08C25/02
CPC分类号： H04L29/06 , H04L69/324
摘要： A system and method are provided for efficiently writing data from one bus device to another bus device across a network. Data packets to be transmitted are ordered and assigned sequence numbers and expected sequence numbers. The expected sequence number of a data packet corresponds to the sequence number of the data packet immediately prior to the current data packet. When a data packet arrives at the receiving bus, its expected sequence number is compared against the sequence numbers of the previous data packets received. If the previously-received data packet bears the sequence number corresponding to the expected sequence number of the newly arrived data packet, the newly arrived data is stored, and an acknowledgement is sent. If a match cannot be found then a retry request message is sent.
摘要翻译：提供了一种系统和方法，用于通过网络有效地将数据从一个总线设备写入另一总线设备。要发送的数据包被排序并分配序列号和预期的序列号。数据分组的期望序列号对应于紧接当前数据分组之前的数据分组的序列号。当数据分组到达接收总线时，将其预期序列号与接收的先前数据分组的序列号进行比较。如果先前接收到的数据分组具有与新到达的数据分组的预期序列号相对应的序列号，则存储新到达的数据，并发送确认。如果无法找到匹配项，则发送重试请求消息。

6. 发明授权

US06804673B2 Access assurance for remote memory access over network 有权
标题翻译：通过网络进行远程存储器访问的访问保证
公开(公告)号：US06804673B2
公开(公告)日：2004-10-12
申请号：US09839954
申请日：2001-04-19
申请人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
发明人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F700
CPC分类号： G06F13/387 , Y10S707/99932
摘要： A method and system provide access assurance regarding an RDMA transaction. The system comprises an initiating device and a target device placed across a network. The initiating device and the target device are coupled to a first and a second buses, respectively. The first and the second buses are coupled to the network router through a first and a second network adaptors. An RDMA space and an associated access assurance space are assigned to the target device in the memory space of the first bus. The initiating device may RDMA the target device by directly reading from or writing into the RDMA space assigned to the target device. To obtain access assurance information regarding the RDMA transaction, the initiator performs a read from the assurance space associated with the RDMA space of the target device in the memory space of the first bus.
摘要翻译：方法和系统提供关于RDMA事务的访问保证。该系统包括通过网络放置的发起设备和目标设备。发起设备和目标设备分别耦合到第一和第二总线。第一和第二总线通过第一和第二网络适配器耦合到网络路由器。 RDMA空间和相关的访问保证空间被分配给第一总线的存储器空间中的目标设备。启动设备可以通过直接从分配给目标设备的RDMA空间读取或写入目标设备来RDMA目标设备。为了获得关于RDMA事务的访问保证信息，启动器从与第一总线的存储器空间中的目标设备的RDMA空间相关联的保证空间执行读取。

7. 发明授权

US06732212B2 Launch raw packet on remote interrupt 有权
标题翻译：在远程中断时启动原始数据包
公开(公告)号：US06732212B2
公开(公告)日：2004-05-04
申请号：US09785071
申请日：2001-02-14
申请人： Hirohide Sugahara , Takashi Miyoshi , Jeffrey D. Larson , Takeshi Horie
发明人： Hirohide Sugahara , Takashi Miyoshi , Jeffrey D. Larson , Takeshi Horie
IPC分类号： G06F1332
CPC分类号： G06F13/24 , G06F2213/2418
摘要： One embodiment of the present invention provides a method for processing a remote interrupt signal or a remote event. Another embodiment of the present invention provides a system for issuing a raw packet over a network in response to a remote interrupt or a remote event. Another embodiment of the present invention provides a network interface system configured to issue interrupt requests over a network.
摘要翻译：本发明的一个实施例提供一种用于处理远程中断信号或远程事件的方法。本发明的另一个实施例提供了一种用于响应于远程中断或远程事件通过网络发出原始分组的系统。本发明的另一个实施例提供一种被配置为通过网络发出中断请求的网络接口系统。

8. 发明授权

US5890217A Coherence apparatus for cache of multiprocessor 失效
标题翻译：多处理器缓存的一致性设备
公开(公告)号：US5890217A
公开(公告)日：1999-03-30
申请号：US598243
申请日：1996-02-07
申请人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
发明人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
IPC分类号： G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F2212/2542
摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
摘要翻译：多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。处理器模块通过第二系统总线相互连接。通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

9. 发明授权

US6038674A Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system 有权
标题翻译：数据传输系统中的多处理器，多处理器，发送和接收器的多处理器，存储器访问方法，数据传输系统和数据传输系统的总线控制方法
公开(公告)号：US6038674A
公开(公告)日：2000-03-14
申请号：US352343
申请日：1999-07-13
申请人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura
发明人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0808
摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.
摘要翻译：多处理器，其中多个处理器经由系统总线连接。多处理器包括每个具有至少一个处理器，主存储器，高速缓冲存储器，高速缓存控制单元，目录存储器和目录控制单元的处理器组。目录控制单元包括无效命令发布单元，其向存储在高速缓存行中的目录存储器中的所有参考指定发出高速缓存行无效命令。因此，可以通过减少从缓存存储器发出高速缓存无效命令的频率来缩短设备处理时间。

10. 发明授权

US5734845A Bus arbiter provided in a multi-processor system 失效
标题翻译：总线仲裁器在多处理器系统中提供
公开(公告)号：US5734845A
公开(公告)日：1998-03-31
申请号：US214590
申请日：1994-03-18
申请人： Hirohide Sugahara
发明人： Hirohide Sugahara
IPC分类号： G06F3/00 , G06F13/14 , G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： In a multi-processor system in which a plurality of units such as a CPU serving as an information processing unit and an I/O control unit can be connected over a system bus, when the plurality of units issue use requests for the system bus, a bus arbiter grants a use authority for the system bus to a specific unit in consideration with priority orders. The bus arbiter is connected to the respective units over at least one specific signal line. The specific signal line conforms to a specific transmission rule in a normal control mode, whereby a specific signal is transmitted over the specific signal line. When a unit is not connected, at least one specific signal line in the bus arbiter is fixed to a state unfeasible in a normal control mode. The specific signal line is monitored if necessary. When the specific signal line linked with a unit is controlled under a specific transmission rule, the unit is recognized as connected. When the specific signal line is fixed to a state unfeasible in a normal control mode, the unit is recognized as unconnected. This obviates the necessity of increasing the number of buses, allows the bus arbiter to distinguish units connected over the system bus from unconnected ones, and realizes a small-sized system.
摘要翻译：在其中可以通过系统总线连接诸如用作信息处理单元的CPU的多个单元和I / O控制单元的多处理器系统中，当多个单元发出对系统总线的使用请求时，考虑到优先级命令，总线仲裁器将系统总线的使用权授予特定单元。总线仲裁器通过至少一个特定信号线连接到相应的单元。特定信号线在正常控制模式下符合特定传输规则，由此特定信号通过特定信号线传输。当单元未连接时，总线仲裁器中的至少一个特定信号线固定为在正常控制模式下不可行的状态。必要时监视特定信号线。当与特定信号链接的单元被控制在特定的传输规则下时，该单元被识别为已连接。当特定信号线固定为在正常控制模式下不可行的状态时，该单元被识别为未连接。这消除了增加总线数量的必要性，允许总线仲裁器区分通过系统总线连接的单元与未连接的总线，并实现小型系统。

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