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1. 发明授权

US6038674A Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system 有权
标题翻译：数据传输系统中的多处理器，多处理器，发送和接收器的多处理器，存储器访问方法，数据传输系统和数据传输系统的总线控制方法
公开(公告)号：US6038674A
公开(公告)日：2000-03-14
申请号：US352343
申请日：1999-07-13
申请人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura
发明人： Takatsugu Sasaki , Akira Kabemoto , Hirohide Sugahara , Junji Nishioka , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F12/0808
摘要： A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.
摘要翻译：多处理器，其中多个处理器经由系统总线连接。多处理器包括每个具有至少一个处理器，主存储器，高速缓冲存储器，高速缓存控制单元，目录存储器和目录控制单元的处理器组。目录控制单元包括无效命令发布单元，其向存储在高速缓存行中的目录存储器中的所有参考指定发出高速缓存行无效命令。因此，可以通过减少从缓存存储器发出高速缓存无效命令的频率来缩短设备处理时间。

2. 发明授权

US5890217A Coherence apparatus for cache of multiprocessor 失效
标题翻译：多处理器缓存的一致性设备
公开(公告)号：US5890217A
公开(公告)日：1999-03-30
申请号：US598243
申请日：1996-02-07
申请人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
发明人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
IPC分类号： G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F2212/2542
摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
摘要翻译：多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。处理器模块通过第二系统总线相互连接。通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

3. 发明授权

US5675467A Circuit mounting unit 失效
标题翻译：电路安装单元
公开(公告)号：US5675467A
公开(公告)日：1997-10-07
申请号：US496112
申请日：1995-06-28
申请人： Hisayuki Nishimura , Shigeru Honda , Naohiro Shibata
发明人： Hisayuki Nishimura , Shigeru Honda , Naohiro Shibata
IPC分类号： G06F1/26 , G06F3/00 , H02H9/00 , H02M3/00 , H02H7/20
CPC分类号： H02H9/004
摘要： The present invention relates to a circuit mounting unit that can prevent a voltage drop and noise occurrence due to current inflow at the time of a hot insertion or withdrawal operation without mounting a capacitor with large capacitance on the side of a main unit. The circuit mounting unit includes a first voltage control unit that controls to increase gradually a voltage supplied to a load voltage converter from the main unit side to a predetermined voltage when the circuit mounting unit is exchangeably inserted into or pulled out of the main unit without halting electric power supplied from the main unit. The circuit mounting unit is mounted onto a printed wiring board on which various elements such as ICs and LSIs are previously mounted to form a predetermined circuit.
摘要翻译：电路安装单元技术领域本发明涉及一种电路安装单元，其可以防止在热插拔操作时由于电流流入而导致的电压降和噪声发生，而不在主单元侧安装具有大电容的电容器。电路安装单元包括第一电压控制单元，当电路安装单元可交换地插入或拉出主单元而不停止时，控制逐渐增加从主单元侧提供给负载电压转换器的电压至预定电压从主机供电的电力。电路安装单元安装在预先安装各种元件（例如IC和LSI）的印刷电路板上以形成预定电路。

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