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    • 5. 发明授权
      US5402377A Semiconductor memory device having a controlled auxiliary decoder 失效
    • Semiconductor memory device having a controlled auxiliary decoder
    • 具有受控辅助解码器的半导体存储器件
    • US5402377A
    • 1995-03-28
    • US243908
    • 1994-05-17
    • Kenichi Ohhata , Hiroaki Nambu , Kazuo Kanetani , Youji Idei , Takeshi Kusunoki , Toru Masuda
    • Kenichi Ohhata , Hiroaki Nambu , Kazuo Kanetani , Youji Idei , Takeshi Kusunoki , Toru Masuda
    • G11C29/00 , G11C29/04 , G11C8/00
    • G11C29/70
    • A semiconductor memory device has a primary memory cell array, a primary decoder having a first circuit producing an intermediate signal from an address signal and a second circuit producing a first cell selection signal from the intermediate signal for selectively driving a word line and a bit line, an auxiliary memory cell array having a plurality of memory cells, each being used for a defective memory cell found in the primary memory cell array, an auxiliary decoder connected to the primary decoder to receive the intermediate signal, a non-volatile memory for storing first information indicating that the primary memory cell array contains a defective memory cell from which a cell defect signal is produced and for storing second information indicating an address of the defective memory cell from which a defective cell address signal is produced, and a control circuit responsive to the cell defect signal and the defective cell address signal for producing a first control signal to be supplied to the second circuit and a second control signal to be supplied to the auxiliary decoder. The primary decoder is prohibited by the first control signal from accessing a defective memory cell having an address represented by the defective cell address signal. The auxiliary decoder produces a second cell selection signal from the intermediate signal under control of the second control signal and of the cell defect signal for selectively accessing a memory cell in the auxiliary memory cell array.
    • 半导体存储器件具有主存储单元阵列，主解码器具有产生来自地址信号的中间信号的第一电路和从该中间信号产生第一单元选择信号的第二电路，用于选择性地驱动字线和位线 ，具有多个存储单元的辅助存储单元阵列，每个存储单元用于存储在主存储单元阵列中的缺陷存储单元，连接到主解码器以接收中间信号的辅助解码器，用于存储的非易失性存储器 指示主存储单元阵列包含产生单元缺陷信号的缺陷存储单元的第一信息，以及用于存储表示产生有缺陷单元地址信号的缺陷存储单元的地址的第二信息，以及响应于控制电路的控制电路 到单元缺陷信号和用于产生第一控制信号的有缺陷单元地址信号 提供给第二电路和第二控制信号以提供给辅助解码器。 主解码器被第一控制信号禁止访问具有由缺陷单元地址信号表示的地址的有缺陷的存储单元。 辅助解码器在第二控制信号和单元缺陷信号的控制下，从中间信号产生第二单元选择信号，用于选择性地访问辅助存储单元阵列中的存储单元。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US6075729A High-speed static random access memory 有权
    • High-speed static random access memory
    • 高速静态随机存取存储器
    • US6075729A
    • 2000-06-13
    • US145161
    • 1998-09-01
    • Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki , Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Keiichi Higeta
    • Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki , Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Keiichi Higeta
    • G11C7/12 , G11C11/412 , G11C7/00
    • G11C11/412 , G11C7/12 , G11C2207/12
    • A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question. The bit line load circuit and the bit line recovery circuit include pMOS transistors whose drains are connected to the bit lines and whose gates are fed with a control signal, and diodes whose anodes are connected to a first power supply and whose cathodes are connected to sources of the pMOS transistors, the pMOS transistors and the diodes being furnished to each of the bit line pairs. The pMOS transistors are inhibited from conducting while the bit lines are being driven Low by the bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a read cycle. This constitution shortens the recovery time, implementing a high-speed SRAM with a shortened cycle time.
    • 半导体存储器具有多个字线，多个位线对和形成在字线和位线对之间的交点处的多个存储单元。 字解码器在接收到地址信号时产生字线选择信号，并且位解码器在接收到地址信号时产生位线选择信号。 位线负载电路从可应用的存储单元接收信号电流，感测电路检测来自位线负载电路的输出信号，位线下拉电路和位线恢复电路在写入时驱动可应用的位线 数据到所讨论的存储单元。 位线负载电路和位线恢复电路包括其漏极连接到位线并且其栅极被馈送控制信号的pMOS晶体管，以及其阳极连接到第一电源并且其阴极连接到源极的二极管 的pMOS晶体管，pMOS晶体管和二极管被提供给每个位线对。 在写周期期间位线被位线下拉电路驱动为低电平时，禁止pMOS晶体管导通，并允许其在包括读周期的其他周期期间导通。 这种结构缩短了恢复时间，实现了一个缩短周期时间的高速SRAM。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US06304357B1 Optical receiver 失效
    • Optical receiver
    • 光接收机
    • US06304357B1
    • 2001-10-16
    • US09041973
    • 1998-03-13
    • Kenichi Ohhata , Ryoji Takeyari , Toru Masuda , Katsuyoshi Washio , Yasushi Hatta
    • Kenichi Ohhata , Ryoji Takeyari , Toru Masuda , Katsuyoshi Washio , Yasushi Hatta
    • H04B1006
    • H04B10/6932 , H04B10/6933 , H04B10/695
    • An optical receiver generates a voltage signal having a predetermined swing from a current signal, and feeds the voltage signal to a decision circuit. An optical receiving element receives the input optical signal, converts the optical signal to a current signal, and provides the current signal to a preamplifier, which converts the input current signal into a voltage signal. The voltage signal is input to an amplifier having a limiting function, which linearly amplifies the voltage signal when the swing of the voltage signal is smaller than a predetermined value, and limitedly amplifies the voltage signal when the voltage signal is greater than the predetermined value. An automatic-gain-control amplifier receives the output from the amplifier with the limiting function, and amplifies the input voltage signal to a voltage signal having a constant swing. The decision circuit receives the output of the automatic-gain-control amplifier and decides the binary nature of the voltage, and thus of the input optical signal.
    • 光接收器从电流信号产生具有预定摆幅的电压信号，并将电压信号馈送到判定电路。 光接收元件接收输入光信号，将光信号转换为电流信号，并将电流信号提供给前置放大器，将前置放大器转换成电压信号。 电压信号被输入到具有限制功能的放大器，当电压信号的摆动小于预定值时线性放大电压信号，并且当电压信号大于预定值时有限地放大电压信号。 自动增益控制放大器以限制功能接收来自放大器的输出，并将输入电压信号放大到具有恒定摆幅的电压信号。 决定电路接收自动增益控制放大器的输出，并确定电压的二进制特性，从而确定输入光信号的二进制特性。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US07212744B2 Receiver circuit and transmitter circuit 失效
    • Receiver circuit and transmitter circuit
    • 接收机电路和发射机电路
    • US07212744B2
    • 2007-05-01
    • US10759101
    • 2004-01-20
    • Nobuhiro Shiramizu , Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki
    • Nobuhiro Shiramizu , Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki
    • H04B10/00 , H04J4/00 , H04L7/00
    • H03K5/00006 , H03M9/00 , H04J3/047 , H04J3/0685
    • The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters.A clock signal synchronized with data at f1/n Hz is converted by a multiplier so that the signal has a frequency of “n” times so as to use the clock signal for triggering a flip-flop the operation frequency of which is f1 b/s in the synchronous digital circuit. The multiplier is arranged in the vicinity of the flip-flop triggered by the clock signal of f1 Hz so as to avoid the effect of the deterioration of the operation frequency by interconnect capacitance.The maximum operation frequency of the transceiver circuit determined based upon the operating frequency of the synchronous digital circuit can be enhanced up to the maximum operation frequency of the flip-flop. As a margin can be produced in designing a frequency band of a clock signal processing circuit, the reduction of power consumption, the reduction of phase noise and the extension of a control frequency range can be realized.
    • 本发明提供一种用于通信的收发器电路，其增强了直到触发器的最大频率的同步数字电路的操作频率，并且抑制了抖动的发生。 与f 1 / n Hz的数据同步的时钟信号由乘法器转换，使得信号具有“n”倍的频率，以便使用用于触发触发器的时钟信号，其操作频率为f 1 b / s在同步数字电路。 乘法器布置在由f1Hz的时钟信号触发的触发器附近，以避免由互连电容引起的工作频率恶化的影响。 基于同步数字电路的工作频率确定的收发器电路的最大工作频率可以增加到触发器的最大工作频率。 由于可以在设计时钟信号处理电路的频带时产生边际，可以实现功耗的降低，相位噪声的降低和控制频率范围的扩展。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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