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1. 发明授权

US07212744B2 Receiver circuit and transmitter circuit 失效
标题翻译：接收机电路和发射机电路
公开(公告)号：US07212744B2
公开(公告)日：2007-05-01
申请号：US10759101
申请日：2004-01-20
申请人： Nobuhiro Shiramizu , Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki
发明人： Nobuhiro Shiramizu , Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki
IPC分类号： H04B10/00 , H04J4/00 , H04L7/00
CPC分类号： H03K5/00006 , H03M9/00 , H04J3/047 , H04J3/0685
摘要： The invention provides a transceiver circuit for communication that enhances the operation frequency of a synchronous digital circuit up to the maximum frequency of a flip-flop and inhibits the occurrence of jitters.A clock signal synchronized with data at f1/n Hz is converted by a multiplier so that the signal has a frequency of “n” times so as to use the clock signal for triggering a flip-flop the operation frequency of which is f1 b/s in the synchronous digital circuit. The multiplier is arranged in the vicinity of the flip-flop triggered by the clock signal of f1 Hz so as to avoid the effect of the deterioration of the operation frequency by interconnect capacitance.The maximum operation frequency of the transceiver circuit determined based upon the operating frequency of the synchronous digital circuit can be enhanced up to the maximum operation frequency of the flip-flop. As a margin can be produced in designing a frequency band of a clock signal processing circuit, the reduction of power consumption, the reduction of phase noise and the extension of a control frequency range can be realized.
摘要翻译：本发明提供一种用于通信的收发器电路，其增强了直到触发器的最大频率的同步数字电路的操作频率，并且抑制了抖动的发生。与f 1 / n Hz的数据同步的时钟信号由乘法器转换，使得信号具有“n”倍的频率，以便使用用于触发触发器的时钟信号，其操作频率为f 1 b / s在同步数字电路。乘法器布置在由f1Hz的时钟信号触发的触发器附近，以避免由互连电容引起的工作频率恶化的影响。基于同步数字电路的工作频率确定的收发器电路的最大工作频率可以增加到触发器的最大工作频率。由于可以在设计时钟信号处理电路的频带时产生边际，可以实现功耗的降低，相位噪声的降低和控制频率范围的扩展。

2. 发明授权

US6075729A High-speed static random access memory 有权
标题翻译：高速静态随机存取存储器
公开(公告)号：US6075729A
公开(公告)日：2000-06-13
申请号：US145161
申请日：1998-09-01
申请人： Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki , Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Keiichi Higeta
发明人： Kenichi Ohhata , Fumihiko Arakawa , Takeshi Kusunoki , Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Keiichi Higeta
IPC分类号： G11C7/12 , G11C11/412 , G11C7/00
CPC分类号： G11C11/412 , G11C7/12 , G11C2207/12
摘要： A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question. The bit line load circuit and the bit line recovery circuit include pMOS transistors whose drains are connected to the bit lines and whose gates are fed with a control signal, and diodes whose anodes are connected to a first power supply and whose cathodes are connected to sources of the pMOS transistors, the pMOS transistors and the diodes being furnished to each of the bit line pairs. The pMOS transistors are inhibited from conducting while the bit lines are being driven Low by the bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a read cycle. This constitution shortens the recovery time, implementing a high-speed SRAM with a shortened cycle time.
摘要翻译：半导体存储器具有多个字线，多个位线对和形成在字线和位线对之间的交点处的多个存储单元。字解码器在接收到地址信号时产生字线选择信号，并且位解码器在接收到地址信号时产生位线选择信号。位线负载电路从可应用的存储单元接收信号电流，感测电路检测来自位线负载电路的输出信号，位线下拉电路和位线恢复电路在写入时驱动可应用的位线数据到所讨论的存储单元。位线负载电路和位线恢复电路包括其漏极连接到位线并且其栅极被馈送控制信号的pMOS晶体管，以及其阳极连接到第一电源并且其阴极连接到源极的二极管的pMOS晶体管，pMOS晶体管和二极管被提供给每个位线对。在写周期期间位线被位线下拉电路驱动为低电平时，禁止pMOS晶体管导通，并允许其在包括读周期的其他周期期间导通。这种结构缩短了恢复时间，实现了一个缩短周期时间的高速SRAM。

3. 发明授权

US06369617B1 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06369617B1
公开(公告)日：2002-04-09
申请号：US09437268
申请日：1999-11-10
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.
摘要翻译：为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为减少通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加的周期被启用。

4. 发明授权

US06677782B2 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 有权
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06677782B2
公开(公告)日：2004-01-13
申请号：US09840190
申请日：2001-04-24
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： H03K19096
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.
摘要翻译：为了加快解码电路的运行，解码电路的功耗降低，周期增加，解码电路中的缓冲器，预解码器，主译码器等电路由半导体逻辑电路构成，用于在输出节点下拉的晶体管的列较小，即使输入数量多，并且获得具有大致相同延迟时间的真实和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为根据本发明，可以加速解码器电路的操作，可以降低功耗，可以增加周期，并且在半导体存储器中，例如，减少访问时间和功耗以及增加的周期被启用。

5. 发明授权

US06229745B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06229745B1
公开(公告)日：2001-05-08
申请号：US09558375
申请日：2000-04-26
申请人： Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki
发明人： Hiroaki Nambu , Kazuo Kanetani , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki
IPC分类号： G11C702
CPC分类号： G11C7/06
摘要： A semiconductor memory in accordance with the present invention includes a sense amplifier composed of a plurality of MOS transistors. When the sense amplifier is on standby, a first control circuit brings an input signal of the sense amplifier to zero. A second control circuit uses voltages developed because of an offset voltage occurring in the sense amplifier to feed back the potentials in the wells of the MOS transistors so that the offset voltage will be nullified. When the offset voltage occurring in the sense amplifier is nullified, a delay time required by the sense amplifier is shortened. This results in the high-speed semiconductor memory.
摘要翻译：根据本发明的半导体存储器包括由多个MOS晶体管组成的读出放大器。当读出放大器处于待机状态时，第一个控制电路使读出放大器的输入信号为零。第二控制电路使用由于读出放大器中发生的偏移电压而产生的电压反馈MOS晶体管的阱中的电位，使得偏移电压将被无效。当读出放大器中发生的失调电压无效时，读出放大器所需的延迟时间缩短。这导致高速半导体存储器。

6. 发明授权

US06998878B2 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06998878B2
公开(公告)日：2006-02-14
申请号：US10754596
申请日：2004-01-12
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： H03K19/20
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.
摘要翻译：为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中，在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是减少利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期增加。

7. 发明授权

US06438050B1 Signal transmission circuit and semiconductor memory using the same 失效
标题翻译：信号传输电路和半导体存储器使用相同
公开(公告)号：US06438050B1
公开(公告)日：2002-08-20
申请号：US10038914
申请日：2002-01-08
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
IPC分类号： G11C700
CPC分类号： H03K3/356139
摘要： A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.
摘要翻译：一种用于通过信号线在电路单元之间传输数据信号的传输电路。发送数据信号，用于在预充电期间将信号线预充电到高电位，并根据在评估期间传输的数据将其放电到低电位，或保持信号线原样。锁存型源耦合逻辑被配置为使得用作下一级的输出端的第一节点和第二节点在预充电周期期间分别充电到高电位。第二节点在评估期间根据第一节点的电位放电，第一节点根据信号线上的电位放电。因此，可以加快由驱动电路对信号线进行放电的动作。

8. 发明申请

US20060119970A1 Semiconductor device and magnetic recording system using the same 审中-公开
标题翻译：半导体器件和使用其的磁记录系统
公开(公告)号：US20060119970A1
公开(公告)日：2006-06-08
申请号：US11291814
申请日：2005-12-02
申请人： Yoshihiro Hayashi , Fumihiko Arakawa , Takeshi Kusunoki , Satoshi Ueno
发明人： Yoshihiro Hayashi , Fumihiko Arakawa , Takeshi Kusunoki , Satoshi Ueno
IPC分类号： G11B5/02 , G11B5/09
CPC分类号： G11B5/02
摘要： A write driver circuit capable of controlling the waveform of overshoot of a write current, more specifically, controlling a rise, amplitude, and duration of overshoot (OS) in the waveform of an output current independently of one another. The write driver circuit includes transistors for controlling the rise, amplitude, and duration of OS, an impedance matching unit between the write driver and the load, and a canceller of reflection waves from the head.
摘要翻译：一种能够控制写入电流的过冲波形的写入驱动器电路，更具体而言，控制输出电流波形中的上升，振幅和持续时间（OS）彼此独立。写驱动器电路包括用于控制OS的上升，振幅和持续时间的晶体管，写入驱动器和负载之间的阻抗匹配单元，以及来自头部的反射波的消除器。

9. 发明授权

US06617610B2 Semiconductor integrated circuit 有权
公开(公告)号：US06617610B2
公开(公告)日：2003-09-09
申请号：US10013474
申请日：2001-12-13
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki , Keiichi Higeta
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Fumihiko Arakawa , Takeshi Kusunoki , Keiichi Higeta
IPC分类号： H01L2358
CPC分类号： G01R31/31701
摘要： In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

10. 发明授权

US06356493B1 Signal transmission circuit and semiconductor memory using the same 失效
标题翻译：信号传输电路和半导体存储器使用相同
公开(公告)号：US06356493B1
公开(公告)日：2002-03-12
申请号：US09636737
申请日：2000-08-11
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Fumihiko Arakawa
IPC分类号： G11C700
CPC分类号： H03K3/356139
摘要： A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic as configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.
摘要翻译：一种用于通过信号线在电路单元之间传输数据信号的传输电路。发送数据信号，用于在预充电期间将信号线预充电到高电位，并根据在评估期间传输的数据将其放电到低电位，或保持信号线原样。锁存型源耦合逻辑被配置为使得用作下一级的输出端的第一节点和第二节点在预充电周期期间分别充电到高电位。第二节点在评估期间根据第一节点的电位放电，第一节点根据信号线上的电位放电。因此，可以加快由驱动电路对信号线进行放电的动作。

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