专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060007855A1 Prioritization of network traffic 有权
标题翻译：网络流量优先排序
公开(公告)号：US20060007855A1
公开(公告)日：2006-01-12
申请号：US10885821
申请日：2004-07-07
申请人： Hieu Tran , Dinesh Kumar , Kiran Patil , Linden Cornett
发明人： Hieu Tran , Dinesh Kumar , Kiran Patil , Linden Cornett
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/10 , H04L47/2433 , H04L47/245 , H04L47/2475
摘要： A plurality of packets associated with a plurality of protocols are received, wherein the plurality of packets are to be processed by a plurality of processors. Packets associated with a first protocol are sent to be processed by at least one of the plurality of processors before sending packets associated with a second protocol to be processed, in response to determining that the packets associated with the first protocol have a higher priority for processing than the packets associated with the first protocol.
摘要翻译：接收与多个协议相关联的多个分组，其中多个分组将被多个处理器处理。响应于确定与第一协议相关联的分组具有较高的处理优先级，发送与第一协议相关联的分组，以在发送与要处理的第二协议相关联的分组之前由多个处理器中的至少一个处理器处理比与第一协议相关联的分组。

2. 发明申请

US20070274658A1 LOOPBACK DEVICE UTILIZING BEND INSENSITIVE OPTICAL FIBER 有权
标题翻译：使用弯曲敏感光纤的环绕设备
公开(公告)号：US20070274658A1
公开(公告)日：2007-11-29
申请号：US11406190
申请日：2006-04-18
申请人： Micah Isenhour , Christopher Lewallen , James Luther , Thomas Theuerkorn , Hieu Tran
发明人： Micah Isenhour , Christopher Lewallen , James Luther , Thomas Theuerkorn , Hieu Tran
IPC分类号： G02B6/00
CPC分类号： G02B6/4465 , G02B6/4475
摘要： A loopback device utilizing bend insensitive optical fiber to facilitate deployment of a connectorized fiber optic distribution cable through small-diameter conduit. A loopback device utilizing bend insensitive optical fiber for use within an optical network to route optical signals transmitted downstream along one or more optical fibers back upstream along the same or other optical fibers for the purpose of the determining the integrity of the downstream and upstream optical paths from a single upstream location. A loopback device including one or more bend insensitive optical fibers, a multi-fiber loopback ferrule and a dust cap for sealing engaging a connector plug attached to a distribution cable or a tether of a pre-engineered distribution cable assembly prior to installation of the distribution cable.
摘要翻译：一种使用弯曲不敏感光纤的环回装置，以便于通过小直径导管部署连接的光纤配线。一种使用弯曲不敏感光纤在光网络内使用的环回装置，用于将沿着一根或多根光纤的下行传输的光信号沿相同或其它光纤向上游传送，以确定下游和上游光路的完整性从单个上游位置。一种环回装置，包括一个或多个弯曲不敏感光纤，多光纤环回套圈和防尘盖，用于在安装分布之前密封连接到分配电缆或预设计布局电缆组件的系绳的连接器插头电缆。

3. 发明申请

US20070120599A1 Multi-operational amplifier system 有权
标题翻译：多运算放大器系统
公开(公告)号：US20070120599A1
公开(公告)日：2007-05-31
申请号：US11652719
申请日：2007-01-11
申请人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin
发明人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin
IPC分类号： H03F3/00
CPC分类号： H03F3/45192 , H03F3/211 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2203/21109 , H03F2203/21145 , H03F2203/45138 , H03F2203/45288 , H03F2203/45541 , H03F2203/45618 , H03F2203/45626 , H03F2203/45722 , H03F2203/45728 , H03F2203/7206 , H03F2203/7215
摘要： A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.
摘要翻译：多运算放大器系统包括多个运算放大器和用于配置多个运算放大器的控制器。运算放大器可以被选择性地配置成单独操作或与其他运算放大器组合运行。运算放大器可能具有不同的公共节点输入。在一个方面，可以从PMOS，N型NMOS和NZ NMOS输入的组中选择不同的输入。运算放大器可以包括被布置为差分对的不同输入。

4. 发明申请

US20060202741A1 Fast start charge pump for voltage regulators 有权
标题翻译：用于稳压器的快速启动电荷泵
公开(公告)号：US20060202741A1
公开(公告)日：2006-09-14
申请号：US11080067
申请日：2005-03-14
申请人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
发明人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M1/36 , H02M1/44
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

5. 发明申请

US20050093615A1 High voltage generation and regulation system for digital multilevel nonvolatile memory 有权
公开(公告)号：US20050093615A1
公开(公告)日：2005-05-05
申请号：US10990786
申请日：2004-11-16
申请人： William Saiki , Hieu Tran , Sakhawat Khan
发明人： William Saiki , Hieu Tran , Sakhawat Khan
IPC分类号： G11C16/30 , H02M3/07 , H03B1/00
CPC分类号： H02M3/07 , G11C16/30
摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

6. 发明申请

US20050052934A1 Unified multilevel cell memory 有权
标题翻译：统一的多层单元格内存
公开(公告)号：US20050052934A1
公开(公告)日：2005-03-10
申请号：US10659226
申请日：2003-09-09
申请人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
发明人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
IPC分类号： G11C11/56 , G11C15/04 , G11C16/22 , G11C16/26 , G11C8/00
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.
摘要翻译：统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。数据或代码可以存储在单独的数组或公共数组中。在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。标记位可能表示通信接口或IO驱动程序类型。感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。统一存储器中包含XCAM（例如，CAM）阵列。包括统一内存并发。

7. 发明申请

US20050024956A1 Column redundancy for digital multilevel nonvolatile memory 有权
标题翻译：数字多级非易失性存储器的列冗余
公开(公告)号：US20050024956A1
公开(公告)日：2005-02-03
申请号：US10628979
申请日：2003-07-28
申请人： Hieu Tran , Sakhawat Khan , William Saiki , George Korsh
发明人： Hieu Tran , Sakhawat Khan , William Saiki , George Korsh
IPC分类号： G11C7/00 , G11C11/56 , G11C29/00 , G11C29/50
CPC分类号： G11C29/50 , G11C11/5621 , G11C16/04 , G11C29/027 , G11C29/50004 , G11C29/82 , G11C2029/0409
摘要： A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.
摘要翻译：数字多电平位存储器阵列系统包括常规存储器阵列和冗余存储器阵列。常规y驱动器对应于每个存储器阵列以将内容读取或写入多级位存储器单元，并将读取的单元内容与参考电压电平进行比较，以确定存储在相应存储器单元中的数据。类似的功能由冗余的y驱动电路执行，用于冗余存储器阵列。在验证存储单元的内容期间，如果读取电压超出参考电压电平的一定余量要求，则实时生成信号，以便不输出来自不良y驱动器的数据和数据从对应于冗余存储器阵列的冗余y驱动器读出。存储器阵列系统还可以包括分数多级冗余。

8. 发明申请

US20050012137A1 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 审中-公开
标题翻译：具有浮动栅极，控制栅极和单独的擦除栅极的非易失性存储单元，这种存储单元的阵列以及制造方法
公开(公告)号：US20050012137A1
公开(公告)日：2005-01-20
申请号：US10622855
申请日：2003-07-18
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.
摘要翻译：具有用于存储电荷的浮动栅极的非易失性存储单元具有控制栅极和单独的擦除栅极。该电池通过热通道电子注入进行编程，并被poly-poly Fowler-Nordheim隧道擦除。公开了一种用于在平面基板中制造单向单元阵列的方法，以及在具有沟槽的基板中的双向单元阵列。还公开了这样的单元阵列和制造这种阵列的方法。

9. 发明申请

US20060182031A1 Techniques to provide recovery receive queues for flooded queues 失效
公开(公告)号：US20060182031A1
公开(公告)日：2006-08-17
申请号：US11061997
申请日：2005-02-17
申请人： Hieu Tran
发明人： Hieu Tran
IPC分类号： H04J1/16 , H04L12/56
CPC分类号： H04L49/9084 , H04L49/90
摘要： In a receive-side scaling compatible environment, techniques to provide at least one recovery receive queue for any receive queue that is full or transferring traffic at too slow a rate.

10. 发明申请

US20060123280A1 Test circuit and method for multilevel cell flash memory 有权
公开(公告)号：US20060123280A1
公开(公告)日：2006-06-08
申请号：US10991702
申请日：2004-11-17
申请人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
发明人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式