专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050052934A1 Unified multilevel cell memory 有权
标题翻译：统一的多层单元格内存
公开(公告)号：US20050052934A1
公开(公告)日：2005-03-10
申请号：US10659226
申请日：2003-09-09
申请人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
发明人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
IPC分类号： G11C11/56 , G11C15/04 , G11C16/22 , G11C16/26 , G11C8/00
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.
摘要翻译：统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。数据或代码可以存储在单独的数组或公共数组中。在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。标记位可能表示通信接口或IO驱动程序类型。感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。统一存储器中包含XCAM（例如，CAM）阵列。包括统一内存并发。

2. 发明申请

US20060044881A1 Unified multilevel cell memory 有权
公开(公告)号：US20060044881A1
公开(公告)日：2006-03-02
申请号：US11229191
申请日：2005-09-15
申请人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
发明人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
IPC分类号： G11C7/10
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

3. 发明申请

US20050201151A1 Unified multilevel cell memory 有权
公开(公告)号：US20050201151A1
公开(公告)日：2005-09-15
申请号：US11126495
申请日：2005-05-10
申请人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
发明人： Hieu Tran , Hung Nguyen , Vishal Sarin , Loc Hoang , Isao Nojima
IPC分类号： G11C11/56 , G11C15/04 , G11C16/22 , G11C16/26 , G11C11/34
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

4. 发明申请

US20060123280A1 Test circuit and method for multilevel cell flash memory 有权
公开(公告)号：US20060123280A1
公开(公告)日：2006-06-08
申请号：US10991702
申请日：2004-11-17
申请人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
发明人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

5. 发明申请

US20060202668A1 Fast voltage regulators for charge pumps 有权
公开(公告)号：US20060202668A1
公开(公告)日：2006-09-14
申请号：US11080070
申请日：2005-03-14
申请人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
发明人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
IPC分类号： G05F5/00 , G05F1/00
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.

6. 发明申请

US20060202741A1 Fast start charge pump for voltage regulators 有权
标题翻译：用于稳压器的快速启动电荷泵
公开(公告)号：US20060202741A1
公开(公告)日：2006-09-14
申请号：US11080067
申请日：2005-03-14
申请人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
发明人： Hieu Tran , Sang Nguyen , Anh Ly , Hung Nguyen , Wingfu Lau , Nasrin Jaffari , Thuan Vu , Vishal Sarin , Loc Hoang
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M1/36 , H02M1/44
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

7. 发明申请

US20060013028A1 High-speed and low-power differential non-volatile content addressable memory cell and array 有权
标题翻译：高速和低功耗差分非易失性内容可寻址存储单元和阵列
公开(公告)号：US20060013028A1
公开(公告)日：2006-01-19
申请号：US10893811
申请日：2004-07-19
申请人： Vishal Sarin , Hieu Tran , Isao Nojima
发明人： Vishal Sarin , Hieu Tran , Isao Nojima
IPC分类号： G11C15/00
CPC分类号： G11C14/00 , G11C15/046
摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.
摘要翻译：差分非易失性内容可寻址存储器阵列具有使用一对非易失性存储元件的差分非易失性内容可寻址存储器单元。每个非易失性存储元件可以是分离栅极浮栅晶体管或堆叠栅极浮栅晶体管，其具有第一端子，第二端子，其间的沟道以及通道的至少一部分上的浮置栅极以控制通道中的电子传导，以及控制栅极。浮置栅极存储晶体管可以处于以下两种状态之一：电流可以在第一端子和第二端子之间流动的第一状态，例如擦除，以及第二状态，诸如编程的，其中基本上没有电流流动在第一端子和第二端子之间。一对差分比较数据线连接到该对非易失性浮栅晶体管中的每一个的控制栅极。匹配线将一对非易失性浮栅晶体管的每一个的第一端连接到第一电压。最后，每个存储元件的第二端子被连接到与第一电压不同的第二电压。通过存储单元的电流表示比较数据线的内容与存储元件的内容之间的错误匹配。

8. 发明申请

US20070165436A1 High-speed and low-power differential non-volatile content addressable memory cell and array 有权
公开(公告)号：US20070165436A1
公开(公告)日：2007-07-19
申请号：US11717922
申请日：2007-03-13
申请人： Vishal Sarin , Hieu Tran , Isao Nojima
发明人： Vishal Sarin , Hieu Tran , Isao Nojima
IPC分类号： G11C7/00 , G11C15/00 , G11C5/14 , G11C7/06
CPC分类号： G11C14/00 , G11C15/046
摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.

9. 发明申请

US20050162230A1 Multi-operational amplifier system 有权
标题翻译：多运算放大器系统
公开(公告)号：US20050162230A1
公开(公告)日：2005-07-28
申请号：US10767248
申请日：2004-01-28
申请人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin
发明人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin
IPC分类号： H03F3/21 , H03F3/45 , H03F3/72
CPC分类号： H03F3/45192 , H03F3/211 , H03F3/45183 , H03F3/45475 , H03F3/72 , H03F2203/21109 , H03F2203/21145 , H03F2203/45138 , H03F2203/45288 , H03F2203/45541 , H03F2203/45618 , H03F2203/45626 , H03F2203/45722 , H03F2203/45728 , H03F2203/7206 , H03F2203/7215
摘要： A multi-operational amplifier system comprises a plurality of operational amplifiers and a controller to configure the plurality of operational amplifiers. The operational amplifiers may be selectively configured to operate individually or in combination with other of the operational amplifiers. The operational amplifiers may have different common node inputs. In one aspect, the different inputs may be selected from groups of PMOS, N-type NMOS and NZ NMOS inputs. The operational amplifiers may include the different inputs that are arranged as differential pairs.
摘要翻译：多运算放大器系统包括多个运算放大器和用于配置多个运算放大器的控制器。运算放大器可以被选择性地配置成单独操作或与其他运算放大器组合运行。运算放大器可能具有不同的公共节点输入。在一个方面，可以从PMOS，N型NMOS和NZ NMOS输入的组中选择不同的输入。运算放大器可以包括被布置为差分对的不同输入。

10. 发明申请

US20060017084A1 Integrated semiconductor metal-insulator-semiconductor capacitor 审中-公开
标题翻译：集成半导体金属绝缘体 - 半导体电容器
公开(公告)号：US20060017084A1
公开(公告)日：2006-01-26
申请号：US10897045
申请日：2004-07-22
申请人： Feng Gao , Changyuan Chen , Vishal Sarin , William Saiki , Hieu Tran , Dana Lee
发明人： Feng Gao , Changyuan Chen , Vishal Sarin , William Saiki , Hieu Tran , Dana Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/0805 , H01L27/0811 , H01L29/94
摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.
摘要翻译：集成的MIS电容器具有两个基本相同的MIS电容器。第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。半导体衬底具有第二导电类型。栅电极与第一电容器的沟道区隔离并隔开。第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。以这种方式，电容器以反并联配置连接。具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式