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1. 发明申请

US20050012137A1 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 审中-公开
标题翻译：具有浮动栅极，控制栅极和单独的擦除栅极的非易失性存储单元，这种存储单元的阵列以及制造方法
公开(公告)号：US20050012137A1
公开(公告)日：2005-01-20
申请号：US10622855
申请日：2003-07-18
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L21/8238
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.
摘要翻译：具有用于存储电荷的浮动栅极的非易失性存储单元具有控制栅极和单独的擦除栅极。该电池通过热通道电子注入进行编程，并被poly-poly Fowler-Nordheim隧道擦除。公开了一种用于在平面基板中制造单向单元阵列的方法，以及在具有沟槽的基板中的双向单元阵列。还公开了这样的单元阵列和制造这种阵列的方法。

2. 发明申请

US20050213386A1 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 有权
公开(公告)号：US20050213386A1
公开(公告)日：2005-09-29
申请号：US11078562
申请日：2005-02-28
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , G11C16/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

3. 发明授权

US07227217B2 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 有权
标题翻译：具有浮动栅极，控制栅极和单独的擦除栅极的非易失性存储单元，这种存储单元的阵列以及制造方法
公开(公告)号：US07227217B2
公开(公告)日：2007-06-05
申请号：US11078562
申请日：2005-02-28
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Van Tran , Dana Lee , Jack E. Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Van Tran , Dana Lee , Jack E. Frayer
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.
摘要翻译：具有用于存储电荷的浮动栅极的非易失性存储单元具有控制栅极和单独的擦除栅极。该电池通过热通道电子注入进行编程，并被poly-poly Fowler-Nordheim隧道擦除。公开了一种用于在平面基板中制造单向单元阵列的方法，以及在具有沟槽的基板中的双向单元阵列。还公开了这样的单元阵列和制造这种阵列的方法。

4. 发明申请

US20080083945A1 SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH PROGRAM/ERASE AND SELECT GATES 有权
标题翻译：具有程序/擦除和选择门的浮动存储器存储器的半导体存储器阵列
公开(公告)号：US20080083945A1
公开(公告)日：2008-04-10
申请号：US11950331
申请日：2007-12-04
申请人： Pavel Klinger , Amitay Levi
发明人： Pavel Klinger , Amitay Levi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
摘要翻译：存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分，第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

5. 发明授权

US07315056B2 Semiconductor memory array of floating gate memory cells with program/erase and select gates 有权
标题翻译：具有编程/擦除和选择门的浮动存储单元的半导体存储器阵列
公开(公告)号：US07315056B2
公开(公告)日：2008-01-01
申请号：US10863030
申请日：2004-06-07
申请人： Pavel Klinger , Amitay Levi
发明人： Pavel Klinger , Amitay Levi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
摘要翻译：存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分，第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

6. 发明授权

US07816723B2 Semiconductor memory array of floating gate memory cells with program/erase and select gates 有权
标题翻译：具有编程/擦除和选择门的浮动存储单元的半导体存储器阵列
公开(公告)号：US07816723B2
公开(公告)日：2010-10-19
申请号：US11950331
申请日：2007-12-04
申请人： Pavel Klinger , Amitay Levi
发明人： Pavel Klinger , Amitay Levi
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
摘要翻译：存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分，第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

7. 发明申请

US20050269622A1 Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same 有权
标题翻译：具有编程/擦除和选择栅极的浮动栅极存储器单元的半导体存储器阵列，以及制造和操作相同的方法
公开(公告)号：US20050269622A1
公开(公告)日：2005-12-08
申请号：US10863030
申请日：2004-06-07
申请人： Pavel Klinger , Amitay Levi
发明人： Pavel Klinger , Amitay Levi
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
摘要翻译：存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分，第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

8. 发明申请

US20080084744A1 METHOD OF MAKING AND OPERATING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH PROGRAM/ERASE AND SELECT GATES 有权
标题翻译：制造和操作具有程序/擦除和选择门的浮动存储器存储器的半导体存储器阵列的方法
公开(公告)号：US20080084744A1
公开(公告)日：2008-04-10
申请号：US11950345
申请日：2007-12-04
申请人： Pavel Klinger , Amitay Levi
发明人： Pavel Klinger , Amitay Levi
IPC分类号： G11C11/34 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/11521 , G11C16/0433 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.
摘要翻译：存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分，第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

9. 发明申请

US20080099789A1 Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby 有权
标题翻译：形成具有源极侧擦除的浮动栅极存储单元的半导体存储器阵列的自对准方法，以及由此制成的存储器阵列
公开(公告)号：US20080099789A1
公开(公告)日：2008-05-01
申请号：US11592104
申请日：2006-11-01
申请人： Alexander Kotov , Amitay Levi , Hung Q. Nguyen , Pavel Klinger
发明人： Alexander Kotov , Amitay Levi , Hung Q. Nguyen , Pavel Klinger
IPC分类号： H01L29/788 , G11C16/04 , H01L21/336 , H01L21/82 , H01L27/10
CPC分类号： H01L27/11521 , G11C16/0425 , H01L29/42324 , H01L29/7885
摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.
摘要翻译：一种形成浮栅存储器单元阵列的方法及由此形成的阵列，其中每个存储单元包括具有第一导电类型的半导体材料的衬底，形成在衬底中的源极和漏极区，设置在该衬底上的导电材料块并且电连接到源极，以及浮置栅极，其具有设置在源极区域上方并与源极区域绝缘的第一部分以及设置在沟道区域上方并与沟道区域绝缘的第二部分。浮动栅极第一部分包括倾斜的上表面和在锐边处相遇的侧表面。导电控制栅极设置在沟道区之上并与沟道区绝缘以控制其导电性。

10. 发明授权

US08138524B2 Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby 有权
标题翻译：形成具有源侧擦除的浮动存储单元的半导体存储器阵列的自对准方法，以及由此制成的存储器阵列
公开(公告)号：US08138524B2
公开(公告)日：2012-03-20
申请号：US11592104
申请日：2006-11-01
申请人： Alexander Kotov , Amitay Levi , Hung Q. Nguyen , Pavel Klinger
发明人： Alexander Kotov , Amitay Levi , Hung Q. Nguyen , Pavel Klinger
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0425 , H01L29/42324 , H01L29/7885
摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.
摘要翻译：一种形成浮栅存储器单元阵列的方法及由此形成的阵列，其中每个存储单元包括具有第一导电类型的半导体材料的衬底，形成在衬底中的源极和漏极区，设置在该衬底上的导电材料块并且电连接到源极，以及浮置栅极，其具有设置在源极区域上方并与源极区域绝缘的第一部分以及设置在沟道区域上方并与沟道区域绝缘的第二部分。浮动栅极第一部分包括倾斜的上表面和在锐边处相遇的侧表面。导电控制栅极设置在沟道区之上并与沟道区绝缘以控制其导电性。

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