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1. 发明授权

US06365513B1 Method of making a semiconductor device including testing before thinning the semiconductor substrate 有权
标题翻译：制造半导体器件的方法包括在稀薄半导体衬底之前的测试
公开(公告)号：US06365513B1
公开(公告)日：2002-04-02
申请号：US09162232
申请日：1998-09-29
申请人： Hidetoshi Furukawa , Atsushi Noma , Tsuyoshi Tanaka , Hidetoshi Ishida , Daisuke Ueda
发明人： Hidetoshi Furukawa , Atsushi Noma , Tsuyoshi Tanaka , Hidetoshi Ishida , Daisuke Ueda
IPC分类号： H01L2166
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.
摘要翻译：在衬底中形成具有底部的通孔，然后在通孔的至少一个侧壁上形成导体层。此后，通过去除衬底的与形成通孔的衬底的另一部分相对的部分使得导体层暴露而使衬底变薄。

2. 发明授权

US07439621B1 Radio frequency signal processing device 失效
标题翻译：射频信号处理装置
公开(公告)号：US07439621B1
公开(公告)日：2008-10-21
申请号：US09707844
申请日：2000-11-08
申请人： Hidetoshi Ishida , Kazuo Miyatsuji , Hidetoshi Furukawa , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hidetoshi Ishida , Kazuo Miyatsuji , Hidetoshi Furukawa , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L23/34 , H01L23/552
CPC分类号： H01L23/552 , H01L27/0207 , H01L27/088 , H01L2223/6644 , H01L2924/0002 , H01L2924/00
摘要： The RF device of the present invention includes: a semiconductor substrate; and first and second semiconductor components provided on the substrate. Each of the components includes source electrodes, a gate electrode and a drain electrode. And multiple through holes, which pass through the substrate in the thickness direction, are opened in a region of the substrate between the two components. To enhance the effect of suppressing electrical interference between the components, a gap between two adjacent ones of the through holes is preferably smaller than the thickness of the substrate.
摘要翻译：本发明的RF器件包括：半导体衬底; 以及设置在基板上的第一和第二半导体部件。每个组件包括源电极，栅电极和漏电极。并且在两个部件之间的基板的区域中打开穿过基板的厚度方向上的多个通孔。为了增强抑制部件之间的电气干扰的效果，两个相邻的通孔之间的间隙优选小于基板的厚度。

3. 发明授权

US06649463B2 Regulating resistor network, semiconductor device including the resistor network, and method for fabricating the device 失效
标题翻译：调节电阻网络，包括电阻网络的半导体器件及其制造方法
公开(公告)号：US06649463B2
公开(公告)日：2003-11-18
申请号：US09754308
申请日：2001-01-05
申请人： Yukio Iwasaki , Hidetoshi Furukawa , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yukio Iwasaki , Hidetoshi Furukawa , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L2120
CPC分类号： H01C17/23 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.
摘要翻译：调节电阻网络包括彼此并联连接的多个电阻器。这些电阻器中的每一个可通过照射光而被切割，并且通过切断至少一个电阻来调整调节电阻网络的电阻值。

4. 发明授权

US06201288B1 Regulating resistor network, semiconductor device including the resistor network, and method for fabricating the device 失效
公开(公告)号：US06201288B1
公开(公告)日：2001-03-13
申请号：US09432107
申请日：1999-11-02
申请人： Yukio Iwasaki , Hidetoshi Furukawa , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yukio Iwasaki , Hidetoshi Furukawa , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L2900
CPC分类号： H01C17/23 , H01L27/0802 , H01L2924/0002 , H01L2924/00
摘要： A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.

5. 发明授权

US06329262B1 Method for producing semiconductor integrated circuit 有权
标题翻译：半导体集成电路的制造方法
公开(公告)号：US06329262B1
公开(公告)日：2001-12-11
申请号：US09256738
申请日：1999-02-24
申请人： Takeshi Fukuda , Hiroshi Takenaka , Hidetoshi Furukawa , Takeshi Fukui , Daisuke Ueda
发明人： Takeshi Fukuda , Hiroshi Takenaka , Hidetoshi Furukawa , Takeshi Fukui , Daisuke Ueda
IPC分类号： H01L2162
CPC分类号： H01L27/0658 , H01L27/0802
摘要： A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor. The semiconductor integrated circuit is provided so as to have a predetermined resistance by measuring electric characteristics of the semiconductor integrated circuit; obtaining a difference between the measured electric characteristics and desired electric characteristics to calculate a required adjusting amount of a resistance of the thermal resistor; and adjusting the resistance of the thermal resistor by the adjusting amount through heating of the thermal resistor with electric power.
摘要翻译：半导体集成电路包括由包含至少约5重量％的硅的钨硅氮化物制成的热电阻器，并且直接或经由绝缘膜形成在半导体衬底上。半导体集成电路通过包括以下步骤的方法制造：在半导体衬底上形成硅化钨化硅膜; 以预定图案图案化硅化钨氮化膜以形成热电阻; 并形成一对要连接到热电阻器的电极。半导体集成电路通过测量半导体集成电路的电特性而具有预定的电阻; 获得所测量的电特性和所需电特性之间的差以计算热敏电阻的电阻的所需调整量; 并且通过用电力加热热敏电阻器来调整热敏电阻的电阻达到调节量。

6. 发明授权

US06245628B1 Method of manufacturing a resistor in a semiconductor device 失效
标题翻译：在半导体器件中制造电阻器的方法
公开(公告)号：US06245628B1
公开(公告)日：2001-06-12
申请号：US09031039
申请日：1998-02-26
申请人： Takeshi Fukui , Hidetoshi Furukawa , Daisuke Ueda
发明人： Takeshi Fukui , Hidetoshi Furukawa , Daisuke Ueda
IPC分类号： H01L21265
CPC分类号： H01L29/66196 , H01L29/8605
摘要： A resistive area 7 is formed selectively on a semi-insulating substrate 1, and ohmic electrodes 10 are formed on both ends of the resistive area. Then a photo resist 14 having an opening 13 between the electrodes 10 is so formed as not completely across the resistive area 7. A desirable resistance value is thus obtained by removing the resistance area 7 by etching through the opening 13 gradually.
摘要翻译：选择性地在半绝缘基板1上形成电阻区域7，并且在电阻区域的两端形成欧姆电极10。然后，在电极10之间具有开口13的光致抗蚀剂14形成为不完全穿过电阻区域7.因此通过逐渐通过开口13进行蚀刻去除电阻区域7，从而获得所需的电阻值。

7. 发明授权

US06025632A Semiconductor integrated circuit with tungston silicide nitride thermal resistor 失效
标题翻译：半导体集成电路与钨硅化硅热电阻
公开(公告)号：US06025632A
公开(公告)日：2000-02-15
申请号：US988799
申请日：1997-12-11
申请人： Takeshi Fukuda , Hiroshi Takenaka , Hidetoshi Furukawa , Takeshi Fukui , Daisuke Ueda
发明人： Takeshi Fukuda , Hiroshi Takenaka , Hidetoshi Furukawa , Takeshi Fukui , Daisuke Ueda
IPC分类号： H01L29/74 , H01L21/822 , H01L23/58 , H01L27/04 , H01L27/06 , H01L27/08 , H01L23/62
CPC分类号： H01L27/0658 , H01L27/0802
摘要： A semiconductor integrated circuit includes a thermal resistor which is made of a tungsten silicon nitride containing at least about 5% by weight of silicon and formed on a semiconductor substrate directly or via an insulating film. The semiconductor integrated circuit is produced by a method including the steps of: forming a tungsten silicide nitride film on a semiconductor substrate; patterning the tungsten silicide nitride film in a predetermined pattern to form a thermal resistor; and forming a pair of electrodes to be connected to the thermal resistor. The semiconductor integrated circuit is provided so as to have a predetermined resistance by measuring electric characteristics of the semiconductor integrated circuit; obtaining a difference between the measured electric characteristics and desired electric characteristics to calculate a required adjusting amount of a resistance of the thermal resistor; and adjusting the resistance of the thermal resistor by the adjusting amount through heating of the thermal resistor with electric power.
摘要翻译：半导体集成电路包括由包含至少约5重量％的硅的钨硅氮化物制成的热电阻器，并且直接或通过绝缘膜形成在半导体衬底上。半导体集成电路通过包括以下步骤的方法制造：在半导体衬底上形成硅化钨化硅膜; 以预定图案图案化硅化钨氮化膜以形成热电阻; 并形成一对要连接到热电阻器的电极。半导体集成电路通过测量半导体集成电路的电特性而具有预定的电阻; 获得测量的电特性和期望的电特性之间的差以计算所需热调节电阻的调整量; 并且通过用电力加热热敏电阻器来调整热敏电阻的电阻达到调节量。

8. 发明授权

US5708292A Power amplification circuit 失效
标题翻译：功率放大电路
公开(公告)号：US5708292A
公开(公告)日：1998-01-13
申请号：US704163
申请日：1996-08-28
申请人： Hidetoshi Furukawa , Daisuke Ueda
发明人： Hidetoshi Furukawa , Daisuke Ueda
IPC分类号： H01L29/04 , H01L29/423 , H03F1/30 , H03F3/193 , H01L31/036
CPC分类号： H03F3/1935 , H01L29/045 , H01L29/42316 , H03F1/306
摘要： Variations in the waveform of high-frequency signals amplified by a field-effect transistor (FET) in a power amplification circuit due to changes in temperature are reduced. A FET having an n-type active layer, a source electrode, a drain electrode and a gate electrode is formed on a (1 0 0)-crystal plane of a semi-insulating GaAs substrate. The FET is protected by a passivation film. The angle .theta., formed between the longitudinal axial direction of the gate electrode and the -direction, is set at an angle of from 0.degree. to 90.degree. corresponding to the impurity concentration of the n-type active layer, in order that the temperature coefficient of the FET threshold voltage becomes substantially equal to the temperature coefficient of the gate bias voltage applied from a power supply to the gate electrode. If the angle .theta. is set at 45.degree., then the temperature coefficient of the FET threshold voltage becomes zero.
摘要翻译：降低了由于温度变化而在功率放大电路中由场效晶体管（FET）放大的高频信号的波形的变化。在半绝缘GaAs衬底的（110°）晶面上形成具有n型有源层，源电极，漏电极和栅电极的FET。 FET由钝化膜保护。形成在栅电极的纵向轴向和<0 -1 -1方向之间的角度θ被设定为对应于n型有源层的杂质浓度的0°至90°的角度，以使FET阈值电压的温度系数基本上等于从电源施加到栅电极的栅偏压的温度系数。如果角度θ设定为45°，则FET阈值电压的温度系数为零。

9. 发明授权

US07439900B2 Radar system with resampling features 有权
标题翻译：雷达系统具有重采样功能
公开(公告)号：US07439900B2
公开(公告)日：2008-10-21
申请号：US11430055
申请日：2006-05-09
申请人： Hidetoshi Furukawa
发明人： Hidetoshi Furukawa
IPC分类号： G01S13/00
CPC分类号： G01S7/2923 , G01S13/28 , G01S13/723
摘要： Disclosed is a radar system which comprises an AD conversion unit for converting an analog signal obtained from an antenna into a digital signal, a frequency analysis unit for performing a frequency analysis of the digital signal converted by the AD conversion unit, a time-frequency analysis unit for performing a time-frequency analysis of the digital signal converted by the AD conversion unit, and a target detection unit for detecting a target based on a signal of which the frequency analysis is performed by the frequency analysis unit and a signal of which the time-frequency analysis is performed by the time-frequency analysis unit.
摘要翻译：本发明公开了一种雷达系统，包括：将从天线获得的模拟信号转换为数字信号的AD转换单元，进行由AD转换单元转换的数字信号的频率分析的频率分析单元，时频分析用于执行由AD转换单元转换的数字信号的时间 - 频率分析的单元，以及用于基于由频率分析单元执行频率分析的信号来检测目标的目标检测单元，以及信号时频分析由时间频率分析单元进行。

10. 发明申请

US20070019698A1 Semiconductor laser device and method for fabricating the same 有权
标题翻译：半导体激光器件及其制造方法
公开(公告)号：US20070019698A1
公开(公告)日：2007-01-25
申请号：US11489616
申请日：2006-07-20
申请人： Toshiya Fukuhisa , Masaya Mannoh , Hidetoshi Furukawa
发明人： Toshiya Fukuhisa , Masaya Mannoh , Hidetoshi Furukawa
IPC分类号： H01S5/00
CPC分类号： H01S5/4031 , B82Y20/00 , H01S5/1039 , H01S5/162 , H01S5/2231 , H01S5/3201 , H01S5/3211 , H01S5/34313 , H01S5/34326 , H01S5/4087
摘要： A semiconductor laser device includes: a first light emitting device, the first light emitting device including a first first-conductive-type cladding layer, a first active layer having a first window region in the vicinity of a light emitting edge surface and a first second-conductive-type cladding layer stacked in this order on a substrate; and a second light emitting device, the second light emitting device including a second first-conductive-type cladding layer, a second active layer having a second window region in the vicinity of a light emitting edge surface and a second second-conductive-type cladding layer stacked in this order on the substrate. In the semiconductor laser device, respective lattice constants of the first second-conductive-type and second second-conductive-type cladding layers are adjusted to compensate for a difference in diffusion rate of an impurity between the first window region in the first active layer and the second window region in the second active layer.
摘要翻译：半导体激光器件包括：第一发光器件，所述第一发光器件包括第一第一导电型包覆层，在发光边缘表面附近具有第一窗口区域的第一有源层和第一第二导电型包层导电型包覆层依次层叠在基板上; 和第二发光器件，所述第二发光器件包括第二第一导电型包覆层，在发光边缘表面附近具有第二窗口区域的第二有源层和第二第二导电型覆层层以此顺序堆叠在基板上。在半导体激光器件中，调整第一第二导电型和第二第二导电型包覆层的各自的晶格常数，以补偿第一有源层中的第一窗口区域和第一有源层之间的杂质的扩散速率的差异第二活动层中的第二窗口区域。

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