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1. 发明申请

US20060224870A1 Information processing device 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20060224870A1
公开(公告)日：2006-10-05
申请号：US11444221
申请日：2006-05-31
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.
摘要翻译：本发明的定义在于，通过流水线处理从指令存储部分读取，缓冲，解码和执行指令的信息处理设备包括：指令读取请求部分，其向指令存储部分分配读取地址; 指令缓冲部分，包括缓冲从指令存储部分读取的指令序列的多个指令缓冲器; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行; 分支指令检测部分，其检测从指令存储部分读取的指令序列中的分支指令; 以及分支目标地址信息缓冲部分，包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息; 其中，当分支指令检测部分已经检测到分支指令时，分支指令的分支目标地址信息被存储在多个分支目标地址信息缓冲器中的一个中，或分支指令的分支目标指令序列被存储除了存储在分支目标地址信息缓冲器之外，还包括在多个指令缓冲器之一中。

2. 发明授权

US07134004B1 Processing device for buffering sequential and target sequences and target address information for multiple branch instructions 失效
标题翻译：用于缓冲顺序和目标序列的处理设备以及多个分支指令的目标地址信息
公开(公告)号：US07134004B1
公开(公告)日：2006-11-07
申请号：US09666853
申请日：2000-09-20
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
摘要翻译：信息处理装置通过流水线处理从指令存储部分读取，缓冲，解码和执行指令，包括：向指令存储部分分配读取地址的指令读取请求部分，包括多个指令缓冲器的指令缓冲部分，缓冲从指令存储部分读取的指令序列; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行。分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息。

3. 发明申请

US20080215859A1 Computer with high-speed context switching 审中-公开
标题翻译：具有高速上下文切换的计算机
公开(公告)号：US20080215859A1
公开(公告)日：2008-09-04
申请号：US12073042
申请日：2008-02-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
IPC分类号： G06F9/312 , G06F9/302
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/461 , G06F9/5016 , G06F2207/5353 , Y02D10/22
摘要： A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.
摘要翻译：以时分方式执行多个程序的并行处理的计算机包括划分为多个区域的硬件资源，记录识别第一程序的识别信息的撤离单元，以及排除存储在所述多个区域的区域中的信息如果该区域是执行第二程序所必需的并被用于执行第一程序的区域，以及恢复单元，其在第二程序停止时基于识别信息将该撤离信息恢复到该区域，或者结束。

4. 发明授权

US06823406B2 Microprocessor executing a program to guarantee an access order 有权
标题翻译：微处理器执行程序来保证访问顺序
公开(公告)号：US06823406B2
公开(公告)日：2004-11-23
申请号：US10095568
申请日：2002-03-13
申请人： Hitoshi Yoda , Hiroyuki Utsumi , Yasuhiro Yamazaki
发明人： Hitoshi Yoda , Hiroyuki Utsumi , Yasuhiro Yamazaki
IPC分类号： G06F1314
CPC分类号： G06F9/3824 , G06F9/3834
摘要： A microprocessor includes a register and a comparator. The register stores an address area, the address area requiring a guarantee of an access order. The comparator compares an address of the address area held in said register with an address of an address area indicated in an access request from CPU, and outputs a signal to execute an access request succeeding the access request from the CPU after executing an access request preceding the access request from the CPU when the address area indicated in the access request from the CPU matches the address area held in said register.
摘要翻译：微处理器包括寄存器和比较器。寄存器存储地址区域，需要保证访问订单的地址区域。比较器将保持在所述寄存器中的地址区域的地址与来自CPU的访问请求中指示的地址区域的地址进行比较，并在执行访问请求之后输出执行来自CPU的访问请求后的访问请求的信号在来自CPU的访问请求中指示的地址区域与保持在所述寄存器中的地址区域匹配时，来自CPU的访问请求之前。

5. 发明授权

US06760810B2 Data processor having instruction cache with low power consumption 有权
标题翻译：具有低功耗指令缓存的数据处理器
公开(公告)号：US06760810B2
公开(公告)日：2004-07-06
申请号：US10023905
申请日：2001-12-21
申请人： Yasuhiro Yamazaki , Taizoh Satoh , Hiroyuki Utsumi , Hitoshi Yoda
发明人： Yasuhiro Yamazaki , Taizoh Satoh , Hiroyuki Utsumi , Hitoshi Yoda
IPC分类号： G06F1200
CPC分类号： G06F12/0882 , G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： The present invention provides a data processor including an instruction cache that can operate at low power consumption, avoiding useless power consumption. The data processor includes a plurality of cache memory units, wherein only a cache memory unit that stores a demanded instruction is enabled, while other memory units are disabled.
摘要翻译：本发明提供了一种数据处理器，其包括能够以低功耗操作的指令高速缓存，避免了无用的功耗。数据处理器包括多个高速缓冲存储器单元，其中只有存储请求指令的高速缓冲存储器单元被启用，而其他存储器单元被禁用。

6. 发明申请

US20080162903A1 Information processing apparatus 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20080162903A1
公开(公告)日：2008-07-03
申请号：US11907617
申请日：2007-10-15
申请人： Yasuhiro Yamazaki
发明人： Yasuhiro Yamazaki
IPC分类号： G06F9/38
CPC分类号： G06F9/322 , G06F9/324 , G06F9/3804 , G06F9/382 , G06F9/3844 , G06F9/3846
摘要： There is provided an information processing apparatus characterized by including: an instruction cache memory storing an instruction; a first adder adding a program counter relative branch target address in an inputted branch instruction and a program counter value, and outputting an absolute branch target address; and a write circuit converting the program counter relative branch target address in the inputted branch instruction into the absolute branch target address and writing a converted branch instruction thereof in the instruction cache memory.
摘要翻译：提供了一种信息处理设备，其特征在于包括：存储指令的指令高速缓存存储器; 在输入的分支指令中加上程序计数器相对分支目标地址的第一加法器和程序计数器值，输出绝对分支目标地址; 以及写入电路，将输入的分支指令中的程序计数器相对分支目标地址转换为绝对分支目标地址，并将其转换的分支指令写入指令高速缓冲存储器。

7. 发明授权

US06411580B1 Storing data on a medium in an optical system 失效
公开(公告)号：US06411580B1
公开(公告)日：2002-06-25
申请号：US09682748
申请日：2001-10-12
申请人： Noboru Kimura , Ronald G. Vitullo , Yasuhiro Yamazaki
发明人： Noboru Kimura , Ronald G. Vitullo , Yasuhiro Yamazaki
IPC分类号： G11B700
CPC分类号： G11B27/3027 , G11B7/0045 , G11B7/00456 , G11B7/005 , G11B7/0079 , G11B7/013 , G11B7/126 , G11B11/10506 , G11B11/10513 , G11B11/10515 , G11B11/1053 , G11B11/10597 , G11B19/00 , G11B19/02 , G11B19/12 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1262 , G11B20/1426 , G11B20/1833 , G11B2007/0006 , G11B2020/1434 , G11B2220/2525
摘要： An encoder converts a binary data word to a binary code word. The encoded bits have first and second binary values at a predetermined clock interval. A pulse generator responds to the encoded bits to generate energizing pulses during each clock interval in which the encoded bits have the first binary value. The energizing pules have a uniform duration less than the clock interval. A laser responds to the energizing pulses for recording on a medium.

8. 发明授权

US5682367A Optical data storage and retrieval system and method 失效
标题翻译：光学数据存储和检索系统及方法
公开(公告)号：US5682367A
公开(公告)日：1997-10-28
申请号：US472158
申请日：1995-06-07
申请人： Noboru Kimura , Ronald G. Vitullo , Yasuhiro Yamazaki
发明人： Noboru Kimura , Ronald G. Vitullo , Yasuhiro Yamazaki
IPC分类号： G11B7/00 , G11B7/0045 , G11B7/005 , G11B7/007 , G11B7/013 , G11B7/125 , G11B11/10 , G11B11/105 , G11B19/00 , G11B19/02 , G11B19/12 , G11B20/10 , G11B20/12 , G11B20/14 , G11B20/18 , G11B27/30
CPC分类号： G11B27/3027 , G11B11/10506 , G11B11/10513 , G11B11/10515 , G11B11/1053 , G11B11/10597 , G11B19/00 , G11B19/02 , G11B19/12 , G11B20/10 , G11B20/10009 , G11B20/1258 , G11B20/1426 , G11B20/1833 , G11B7/0045 , G11B7/00456 , G11B7/005 , G11B7/007 , G11B7/00745 , G11B7/0079 , G11B7/013 , G11B7/126 , G11B20/1262 , G11B2007/0006 , G11B2020/1434 , G11B2220/2525
摘要： A first write encoder encodes digital data in a first, high-density format. A second write encoder encodes digital data in a second, low-density (i.e., ANSI) format. A first read decoder decodes digital data from the first format. A second read decoder decodes digital data from the second format. A disk drive receives a replaceable 90 millimeter optical disk. A read/write head reads encoded data from and writes encoded data to a 90 millimeter optical disk received by the drive. In a first mode, the first write encoder is connected between a source of digital data and the read/write head, and the first read decoder is connected between the read/write head and the utilizing apparatus. In a second mode, the second write encoder is connected between the source and the read/write head, and the second read decoder is connected between the read/write head and the utilizing apparatus. Control electronics switch between the first and second modes, depending upon the format in which data is recorded on the disk received by the disk drive. An 8/9 GCR encoder and a laser pulse generator are used in the first write encoder to record data on the optical media to increase the storage capacity. Improvement in timing is accomplished with write compensation and signal equalization.
摘要翻译：第一写入编码器以第一高密度格式对数字数据进行编码。第二个写入编码器以第二个低密度（即ANSI）格式编码数字数据。第一读取解码器从第一格式解码数字数据。第二读取解码器从第二格式解码数字数据。磁盘驱动器接收可更换的90毫米光盘。读/写头读取编码数据并将编码数据写入由驱动器接收的90毫米光盘。在第一模式中，第一写入编码器连接在数字数据源和读/写头之间，第一读取解码器连接在读/写头与利用装置之间。在第二模式中，第二写入编码器连接在源和读/写头之间，第二读取解码器连接在读/写头与利用装置之间。控制电子设备在第一和第二模式之间切换，这取决于磁盘驱动器接收的磁盘上数据记录的格式。在第一写入编码器中使用8/9 GCR编码器和激光脉冲发生器来在光学介质上记录数据以增加存储容量。通过写入补偿和信号均衡来实现时序的改进。

9. 发明授权

US4652935A Graded facsimile image signal coding system 失效
标题翻译：分级传真图像信号编码系统
公开(公告)号：US4652935A
公开(公告)日：1987-03-24
申请号：US833370
申请日：1986-02-25
申请人： Toshiaki Endoh , Yasuhiro Yamazaki
发明人： Toshiaki Endoh , Yasuhiro Yamazaki
IPC分类号： H04N1/41 , H04N1/417 , H04N1/40
CPC分类号： H04N1/4172
摘要： A graded facsimile image signal coding system is disclosed which is provided with means for distributing a multi-graded facsimile picture signal, represented by 2.sup.n gradation levels, into n bit planes corresponding to n digits; initial encoding means for detecting, from picture elements forming each bit plane, picture elements at intervals of .DELTA.X picture elements on every .DELTA.Y-th line and encoding the detected picture elements; and additional coding means for further coding each one of said encoded picture elements with reference to encoded four picture elements positioned around said one picture element to be coded.
摘要翻译：公开了一种分级传真图像信号编码系统，其具有用于将由2n个灰度等级表示的多分辨率传真图像信号分配到对应于n个数字的n个比特平面中的装置; 初始编码装置，用于从每个DELTA Y线上的DELTA X像素的间隔检测形成每个比特平面的图像元素，并对所检测的图像元素进行编码; 以及附加编码装置，用于参考围绕所述待编码的一个像素周围的编码的四个图像元素进一步编码所述编码图像元素中的每一个。

10. 发明授权

US4134133A Method for interline-coding facsimile signal 失效
标题翻译：传真信号间线编码方法
公开(公告)号：US4134133A
公开(公告)日：1979-01-09
申请号：US817421
申请日：1977-07-20
申请人： Hiroichi Teramura , Yasuhiro Yamazaki , Yasushi Wakahara
发明人： Hiroichi Teramura , Yasuhiro Yamazaki , Yasushi Wakahara
IPC分类号： G06T9/00 , H04N1/417 , H04N1/40 , H04N7/12
CPC分类号： H04N1/417 , G06T9/004
摘要： A method for interline-coding a facsimile signal, in which information of scanning lines of the input facsimile signal is alternately divided into information of at least one first unit line and information of at least one second unit line. A first one of the first unit lines is first coded in accordance with a predetermined coding principle. The information of the next one of the first unit lines is secondly coded in accordance with a predetermined coding principle prior to coding of information of the first one of said second unit lines. The information of the first one of the second unit lines is thirdly coded by two-dimensional predictive coding using, as reference information, the information of the first one and the next one of the first unit lines. The operations of the second coding and the operation of the third coding are repeatedly achieved thereafter.
摘要翻译：一种用于对传真信号进行行间编码的方法，其中将输入传真信号的扫描线的信息交替划分为至少一个第一单元行的信息和至少一个第二单位行的信息。首先根据预定的编码原理对第一单元线进行编码。在对第一单元线中的第一单元线的信息进行编码之前，根据预定的编码原理对下一个第一单元行的信息进行二次编码。第二单元行中的第一单元行的信息通过使用第一单元行中的第一单元行和下一个单元行的信息作为参考信息的二维预测编码进行第三编码。此后重复实现第二编码的操作和第三编码的操作。

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