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1. 发明申请

US20060124982A1 Low-Cost Deep Trench Decoupling Capacitor Device and Process of Manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US20060124982A1
公开(公告)日：2006-06-15
申请号：US10905094
申请日：2004-12-15
申请人： Herbert Ho , John Barth , Ramachandra Divakaruni , Wayne Ellis , Johnathan Faltermeier , Brent Anderson , Subramanian Iyer , Deok-Kee Kim , Randy Mann , Paul Parries
发明人： Herbert Ho , John Barth , Ramachandra Divakaruni , Wayne Ellis , Johnathan Faltermeier , Brent Anderson , Subramanian Iyer , Deok-Kee Kim , Randy Mann , Paul Parries
IPC分类号： H01L29/94 , H01L27/108
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

2. 发明授权

US07413833B2 Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask 有权
标题翻译：使用交替的相移掩模对具有线和间隔阵列的掩模级的单次曝光
公开(公告)号：US07413833B2
公开(公告)日：2008-08-19
申请号：US10846275
申请日：2004-05-14
申请人： Shahid Butt , Scott Bukofsky , Ramachandra Divakaruni , Carl Radens , Wayne Ellis
发明人： Shahid Butt , Scott Bukofsky , Ramachandra Divakaruni , Carl Radens , Wayne Ellis
IPC分类号： G03F1/00
CPC分类号： G03F1/30 , H01L21/3083 , H01L21/32139 , H01L27/0207 , H01L27/1087 , H01L27/10882
摘要： An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated. At the opposite end of the array, the lines that have the opposite phase shift extend into the support region, and the lines of having the respective phase shift are terminated.
摘要翻译：使用替代的相移掩模，通过单次曝光在深沟槽图案之上形成有源区域图案。为了防止相对相位的相邻空间在有源区域图案的基本不透明特征的端部彼此相交，使用一个或多个连接器来连接基本不透明图案的端部。深沟槽图案的沟槽区域布置成使得连接器的传导路径被中断，并且防止线路彼此短路。或者，使用交替相移掩模以单次曝光印刷具有线和间隔阵列的位线图案或字线图案和支撑区域。在阵列区域的一端，具有各自的相移的线延伸到支撑区域，并且相反相移的线路终止。在阵列的相对端，具有相反相移的线延伸到支撑区域中，并且具有相应相移的线路终止。

3. 发明申请

US20050255387A1 Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask 有权
标题翻译：使用交替的相移掩模对具有线和间隔阵列的掩模级的单次曝光
公开(公告)号：US20050255387A1
公开(公告)日：2005-11-17
申请号：US10846275
申请日：2004-05-14
申请人： Shahid Butt , Scott Bukofsky , Ramachandra Divakaruni , Carl Radens , Wayne Ellis
发明人： Shahid Butt , Scott Bukofsky , Ramachandra Divakaruni , Carl Radens , Wayne Ellis
IPC分类号： G03C5/00 , G03F1/00 , G03F9/00 , H01L21/308 , H01L21/3213 , H01L21/8242 , H01L27/02
CPC分类号： G03F1/30 , H01L21/3083 , H01L21/32139 , H01L27/0207 , H01L27/1087 , H01L27/10882
摘要： An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated. At the opposite end of the array, the lines that have the opposite phase shift extend into the support region, and the lines of having the respective phase shift are terminated.
摘要翻译：使用替代的相移掩模，通过单次曝光在深沟槽图案之上形成有源区域图案。为了防止相对相位的相邻空间在有源区域图案的基本不透明特征的端部彼此相交，使用一个或多个连接器来连接基本不透明图案的端部。深沟槽图案的沟槽区域布置成使得连接器的传导路径被中断，并且防止线路彼此短路。或者，使用交替相移掩模以单次曝光印刷具有线和间隔阵列的位线图案或字线图案和支撑区域。在阵列区域的一端，具有相应相移的线延伸到支撑区域，并且相反相移的线路终止。在阵列的相对端，具有相反相移的线延伸到支撑区域中，并且具有相应相移的线路终止。

4. 发明授权

US06670667B2 Asymmetric gates for high density DRAM 失效
公开(公告)号：US06670667B2
公开(公告)日：2003-12-30
申请号：US10213061
申请日：2002-08-06
申请人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
发明人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
IPC分类号： H01L27108
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/4983
摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

5. 发明授权

US06458646B1 Asymmetric gates for high density DRAM 失效
标题翻译：用于高密度DRAM的非对称门
公开(公告)号：US06458646B1
公开(公告)日：2002-10-01
申请号：US09608019
申请日：2000-06-30
申请人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
发明人： Ramachandra Divakaruni , Wayne Ellis , Jack Mandelman , Mary Weybright
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/4983
摘要： A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.
摘要翻译：一种存储器件结构，包括其中形成有一个或多个非对称栅极的阵列器件区域，其中每个非对称栅极包括具有基本上垂直的侧壁的第一边缘和具有多晶硅台阶段的第二边缘，以及包括一个或多个形成在其中的图案化栅极导体，其中支撑装置区域中的每个图案化栅极导体包括具有基本垂直侧壁的边缘。该结构还可以包括位于阵列器件区域和支撑器件区域之间的电路器件区域，所述芯部器件区域包括一个或多个图案化栅极，每个栅极包括在栅极的每一侧上的多晶硅阶梯段。

6. 发明申请

US20070121370A1 SRAM VOLTAGE CONTROL FOR IMPROVED OPERATIONAL MARGINS 有权
标题翻译：用于改进操作标准的SRAM电压控制
公开(公告)号：US20070121370A1
公开(公告)日：2007-05-31
申请号：US11164556
申请日：2005-11-29
申请人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
发明人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
IPC分类号： G11C11/00
CPC分类号： G11C5/14 , G11C11/413
摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.
摘要翻译：提供了包括以阵列布置的多个SRAM单元的静态随机存取存储器（“SRAM”）。阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的多个电压控制。多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于所选列列的多个SRAM单元的电源输入的电压的功能 SRAM。选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。

7. 发明申请

US20080089116A1 SRAM voltage control for improved operational margins 有权
公开(公告)号：US20080089116A1
公开(公告)日：2008-04-17
申请号：US11998948
申请日：2007-12-03
申请人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
发明人： Wayne Ellis , Randy Mann , David Wager , Robert Wong
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C5/14 , G11C11/413
摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

8. 发明申请

US20080189480A1 Memory configured on a common substrate 有权
标题翻译：存储器配置在公共基板上
公开(公告)号：US20080189480A1
公开(公告)日：2008-08-07
申请号：US11701006
申请日：2007-02-01
申请人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
发明人： Jung Pill Kim , Jong-Hoon Oh , Oliver Kiehl , Josef Schnell , Klaus Hummler , Wayne Ellis , Octavian Beldiman , Lee Collins
IPC分类号： G06F12/00
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H05K1/181 , H01L2224/0401
摘要： A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
摘要翻译：存储器包括第一宏芯片，脊芯片和公共基板。公共基板被配置为在第一宏芯片和脊芯片之间传递信号。第一个宏芯片，脊椎芯片和公共基板提供了一个记忆。

9. 外观设计

USD680420S1 Snap hook 有权
公开(公告)号：USD680420S1
公开(公告)日：2013-04-23
申请号：US29409968
申请日：2011-12-30
申请人： Wayne Ellis
设计人： Wayne Ellis

10. 发明授权

US08315099B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08315099B2
公开(公告)日：2012-11-20
申请号：US12844477
申请日：2010-07-27
申请人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
发明人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
IPC分类号： G11C16/04
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一其他。

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