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1. 发明授权

US09064063B1 Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints 有权
标题翻译：用于实现复杂约束的交互式，实时检查或验证的方法，系统和制造
公开(公告)号：US09064063B1
公开(公告)日：2015-06-23
申请号：US13445860
申请日：2012-04-12
申请人： Henry Yu , Joshua Baudhuin , Regis Colwell , Harsh Deshmane , Elias L. Fallon , Sanjib Ghosh , Anjna Khanna , Yinnie Lee , Harindranath Parameswaran , Pardeep Juneja , Roland Ruehl , Simon Simonian , Hui Xu , Timothy Rosek
发明人： Henry Yu , Joshua Baudhuin , Regis Colwell , Harsh Deshmane , Elias L. Fallon , Sanjib Ghosh , Anjna Khanna , Yinnie Lee , Harindranath Parameswaran , Pardeep Juneja , Roland Ruehl , Simon Simonian , Hui Xu , Timothy Rosek
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/06
摘要： Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.
摘要翻译：公开了包括用于实现约束的交互式检查的方法，系统，计算机程序产品。各种实施方案通过绑定器映射过程桥接原理图设计环境和布局环境，并利用原理图设计中的连接信息在物理设计阶段早期识别约束违规。该方法识别或创建布局，并识别或生成修改过程的对象。该方法可以获取设计数据库的快照，或者可以使用一个或多个日志来恢复设计数据库。该方法然后识别或创建便笺本，并对对象执行修改过程以生成更改。该方法在修改过程中使用暂存器和触发器执行约束检查，以在向持久性数据库提交更改之前提供响应于修改过程的交互式反馈。

2. 发明授权

US08694943B1 Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness 有权
标题翻译：用于实现具有连通性和约束意识的电子设计的方法，系统和计算机程序产品
公开(公告)号：US08694943B1
公开(公告)日：2014-04-08
申请号：US13445874
申请日：2012-04-12
申请人： Henry Yu , Roland Ruehl , Elias L. Fallon , Regis Colwell , Joshua Baudhuin , Hui Xu , Harsh Deshmane , Yinnie Lee , Simon Simonian , Harindranath Parameswaran , Pardeep Juneja , Anjna Khanna , Sanjib Ghosh , Timothy Rosek
发明人： Henry Yu , Roland Ruehl , Elias L. Fallon , Regis Colwell , Joshua Baudhuin , Hui Xu , Harsh Deshmane , Yinnie Lee , Simon Simonian , Harindranath Parameswaran , Pardeep Juneja , Anjna Khanna , Sanjib Ghosh , Timothy Rosek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.
摘要翻译：公开了用于实现约束和连接感知物理设计的方法和系统。该方法或系统提供了实现电子设计的连接感知环境。例如，该方法通过在一些实施例中在创建电子设计的同时以几乎实时的方式交互地确定电子设计是否符合各种约束。该方法或系统使用由连接引擎提供的或由设计者指定的连接信息，以向用户呈现关于新创建的对象或新修改的对象是否以交互方式或几乎实时的方式来遵守或违反某些相关约束的反馈，时间，而不必在批处理模式下执行这种约束检查。该方法还使得能够通过使用连接信息来实现电子设计，而不在布局或重建网络上执行提取。

3. 发明授权

US08555237B1 Method and apparatus for design rule violation reporting and visualization 有权
标题翻译：设计规则违规报告和可视化的方法和装置
公开(公告)号：US08555237B1
公开(公告)日：2013-10-08
申请号：US13542424
申请日：2012-07-05
申请人： Pardeep Juneja , Om Kanwar , Harindranath Parameswaran
发明人： Pardeep Juneja , Om Kanwar , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An apparatus and method for reporting design rule violations of an integrated circuit design includes collecting data from a design rule checker module, processing the data, and displaying design rule violations onto the layout. The display of the design rule violations may be interactive by including hypertext links to specifications, text bubbles with violation explanations, measurements, highlighting areas of the layout corresponding to a particular rule, and providing hierarchically expandable nodes for constraint violations in a browser.
摘要翻译：用于报告设计规则违反集成电路设计的装置和方法包括从设计规则检验器模块收集数据，处理数据以及将设计规则违规显示在布局上。设计规则违规的显示可以通过包括规范的超文本链接，具有违规说明的文本气泡，测量，与特定规则相对应的布局的突出显示区域以及在浏览器中提供用于约束违规的分层可扩展节点来交互。

4. 发明授权

US08711177B1 Generation, display, and manipulation of measurements in computer graphical designs 有权
标题翻译：在计算机图形设计中生成，显示和操纵测量
公开(公告)号：US08711177B1
公开(公告)日：2014-04-29
申请号：US13034571
申请日：2011-02-24
申请人： Chayan Majumder , Donald J. O'Riordan , Harindranath Parameswaran
发明人： Chayan Majumder , Donald J. O'Riordan , Harindranath Parameswaran
IPC分类号： G09G5/00
CPC分类号： G06F17/5081
摘要： Display of measurements in a graphical design on a computer system. In one aspect, shapes are displayed in an image, and a definition of a defined area of the image is received. One or more measurements are determined for one or more of the shapes displayed within the predefined area, the one or more measurements determined automatically without a user designating endpoints for the measurements. The one or more measurements are displayed as being associated with the one or more shapes.
摘要翻译：在计算机系统的图形设计中显示测量。在一个方面，形状被显示在图像中，并且接收图像的定义区域的定义。对于在预定义区域内显示的一种或多种形状来确定一个或多个测量结果，一个或多个测量自动确定，而用户不指定测量的端点。一个或多个测量被显示为与一个或多个形状相关联。

5. 发明授权

US08813006B1 Accelerated characterization of circuits for within-die process variations 有权
标题翻译：电路内部加速表征模内工艺变化
公开(公告)号：US08813006B1
公开(公告)日：2014-08-19
申请号：US12055505
申请日：2008-03-26
申请人： Harindranath Parameswaran , Sachin Shrivastava
发明人： Harindranath Parameswaran , Sachin Shrivastava
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more timing arcs to reduce the number of simulations to characterize the subcircuit.
摘要翻译：在本发明的一个实施例中，公开了一种用于电子电路设计的方法。该方法包括分析子电路的网表以确定一个或多个输入引脚和一个或多个输出引脚; 形成所述子电路的弧形图，其包括所述一个或多个输入引脚与所述一个或多个输出引脚之间的一个或多个定时弧; 并且减少晶体管的数量以扰乱以在一个或多个定时弧上的管芯工艺变化内执行灵敏度分析，以减少用于表征子电路的仿真次数。

6. 发明申请

US20100083202A1 METHOD AND SYSTEM FOR PERFORMING IMPROVED TIMING WINDOW ANALYSIS 有权
标题翻译：用于执行改进的时序窗口分析的方法和系统
公开(公告)号：US20100083202A1
公开(公告)日：2010-04-01
申请号：US12241278
申请日：2008-09-30
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.
摘要翻译：公开了一种使用一阶参数化分析建模进行串扰分析的方法，系统和计算机程序产品。该方法可用于考虑定时窗口定义中过程变化的影响。这种方法允许人们绕过与使用定时窗口的最佳情况/最差情况分析相关的简单假设，并提供时序窗口对噪声分析的影响的真实图像。可以根据各个过程参数来查看计时窗口。过程参数可以是实际过程参数，也可以是基于实际过程参数的虚拟/计算组件。过程参数可用于计算用于执行噪声分析的定时窗口的重叠。

7. 发明授权

US08612199B2 Netlist partitioning for characterizing effect of within-die variations 有权
标题翻译：用于表征模内变化影响的网表分区
公开(公告)号：US08612199B2
公开(公告)日：2013-12-17
申请号：US11961787
申请日：2007-12-20
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.
摘要翻译：提出了用于确定过程变化对具有多个设备的集成电路的泄漏的影响的技术。使用设备的工艺参数的第一组值来模拟电路的操作，并且还利用变化的一些过程参数值来模拟电路的操作。对于具有不同值的仿真，电路被分成不同的组件（例如通道耦合组件，CCC），其中每个组件具有一个或多个设备，以及在两个或更多个设备中的每一个中的设备中的过程参数值这些组件是多样的。

8. 发明授权

US08086983B2 Method and system for performing improved timing window analysis 有权
标题翻译：执行改进的时序窗口分析的方法和系统
公开(公告)号：US08086983B2
公开(公告)日：2011-12-27
申请号：US12241278
申请日：2008-09-30
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.
摘要翻译：公开了一种使用一阶参数化分析建模进行串扰分析的方法，系统和计算机程序产品。该方法可用于考虑定时窗口定义中过程变化的影响。这种方法允许人们绕过与使用定时窗口的最佳情况/最差情况分析相关的简单假设，并提供时序窗口对噪声分析的影响的真实图像。可以根据各个过程参数来查看计时窗口。过程参数可以是实际过程参数，也可以是基于实际过程参数的虚拟/计算组件。过程参数可用于计算用于执行噪声分析的定时窗口的重叠。

9. 发明申请

US20090164194A1 Netlist Partitioning for Characterizing Effect of Within-Die Variations 有权
标题翻译：用于表征内部变化影响的网表分区
公开(公告)号：US20090164194A1
公开(公告)日：2009-06-25
申请号：US11961787
申请日：2007-12-20
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.
摘要翻译：提出了用于确定过程变化对具有多个设备的集成电路的泄漏的影响的技术。使用设备的工艺参数的第一组值来模拟电路的操作，并且还利用变化的一些过程参数值来模拟电路的操作。对于具有不同值的仿真，电路被分成不同的组件（例如通道耦合组件，CCC），其中每个组件具有一个或多个设备，以及在两个或更多个设备中的每一个中的设备中的过程参数值这些组件是多样的。

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