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1. 发明授权

US09064063B1 Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints 有权
标题翻译：用于实现复杂约束的交互式，实时检查或验证的方法，系统和制造
公开(公告)号：US09064063B1
公开(公告)日：2015-06-23
申请号：US13445860
申请日：2012-04-12
申请人： Henry Yu , Joshua Baudhuin , Regis Colwell , Harsh Deshmane , Elias L. Fallon , Sanjib Ghosh , Anjna Khanna , Yinnie Lee , Harindranath Parameswaran , Pardeep Juneja , Roland Ruehl , Simon Simonian , Hui Xu , Timothy Rosek
发明人： Henry Yu , Joshua Baudhuin , Regis Colwell , Harsh Deshmane , Elias L. Fallon , Sanjib Ghosh , Anjna Khanna , Yinnie Lee , Harindranath Parameswaran , Pardeep Juneja , Roland Ruehl , Simon Simonian , Hui Xu , Timothy Rosek
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/06
摘要： Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.
摘要翻译：公开了包括用于实现约束的交互式检查的方法，系统，计算机程序产品。各种实施方案通过绑定器映射过程桥接原理图设计环境和布局环境，并利用原理图设计中的连接信息在物理设计阶段早期识别约束违规。该方法识别或创建布局，并识别或生成修改过程的对象。该方法可以获取设计数据库的快照，或者可以使用一个或多个日志来恢复设计数据库。该方法然后识别或创建便笺本，并对对象执行修改过程以生成更改。该方法在修改过程中使用暂存器和触发器执行约束检查，以在向持久性数据库提交更改之前提供响应于修改过程的交互式反馈。

2. 发明授权

US08694943B1 Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness 有权
标题翻译：用于实现具有连通性和约束意识的电子设计的方法，系统和计算机程序产品
公开(公告)号：US08694943B1
公开(公告)日：2014-04-08
申请号：US13445874
申请日：2012-04-12
申请人： Henry Yu , Roland Ruehl , Elias L. Fallon , Regis Colwell , Joshua Baudhuin , Hui Xu , Harsh Deshmane , Yinnie Lee , Simon Simonian , Harindranath Parameswaran , Pardeep Juneja , Anjna Khanna , Sanjib Ghosh , Timothy Rosek
发明人： Henry Yu , Roland Ruehl , Elias L. Fallon , Regis Colwell , Joshua Baudhuin , Hui Xu , Harsh Deshmane , Yinnie Lee , Simon Simonian , Harindranath Parameswaran , Pardeep Juneja , Anjna Khanna , Sanjib Ghosh , Timothy Rosek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.
摘要翻译：公开了用于实现约束和连接感知物理设计的方法和系统。该方法或系统提供了实现电子设计的连接感知环境。例如，该方法通过在一些实施例中在创建电子设计的同时以几乎实时的方式交互地确定电子设计是否符合各种约束。该方法或系统使用由连接引擎提供的或由设计者指定的连接信息，以向用户呈现关于新创建的对象或新修改的对象是否以交互方式或几乎实时的方式来遵守或违反某些相关约束的反馈，时间，而不必在批处理模式下执行这种约束检查。该方法还使得能够通过使用连接信息来实现电子设计，而不在布局或重建网络上执行提取。

3. 发明授权

US08555223B1 Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping 有权
公开(公告)号：US08555223B1
公开(公告)日：2013-10-08
申请号：US13445832
申请日：2012-04-12
申请人： Henry Yu , Joshua Baudhuin , Timothy Rosek , Hui Xu
发明人： Henry Yu , Joshua Baudhuin , Timothy Rosek , Hui Xu
IPC分类号： G06F17/50
摘要： Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.

4. 发明授权

US08595662B1 Methods, systems, and articles of manufacture for implementing a physical design of an electronic circuit with automatic snapping 有权
标题翻译：用于实现具有自动卡扣的电子电路的物理设计的方法，系统和制品
公开(公告)号：US08595662B1
公开(公告)日：2013-11-26
申请号：US13445832
申请日：2012-04-12
申请人： Henry Yu , Joshua Baudhuin , Timothy Rosek , Hui Xu
发明人： Henry Yu , Joshua Baudhuin , Timothy Rosek , Hui Xu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/06
摘要： Disclosed are methods and systems for providing a constraint-driven environment for implementing a physical design of an electronic circuit with automatic snapping. In some embodiments, the method identifies or creates an incomplete layout. The method identifies an object and constraints for the object. The method then identifies an approximate position for the object in the layout and automatically snaps the object to a drop location based on the approximate position while complying with relevant constraint(s). The method may further align an object with another object with some spacing in between in some embodiments. The method may also perform automatic layer-to-layer snapping between two sets of objects such as cell instances, each having at least one object on multiple layers.
摘要翻译：公开了用于提供用于实现具有自动捕捉的电子电路的物理设计的约束驱动环境的方法和系统。在一些实施例中，该方法识别或创建不完整的布局。该方法标识对象和对象的约束。然后，该方法识别布局中对象的大致位置，并且在符合相关约束的情况下，基于近似位置自动将对象锁定到放置位置。在一些实施例中，该方法可以进一步将对象与另一对象在其间具有一定间隔。该方法还可以在诸如单元实例的两组对象之间执行自动层到层捕捉，每个对象在多个层上具有至少一个对象。

5. 发明授权

US07945890B2 Registry for electronic design automation of integrated circuits 有权
标题翻译：集成电路电子设计自动化注册
公开(公告)号：US07945890B2
公开(公告)日：2011-05-17
申请号：US11932062
申请日：2007-10-31
申请人： Regis Colwell , Gilles S. C. Lamant , Alisa Yurovsky , Timothy Rosek
发明人： Regis Colwell , Gilles S. C. Lamant , Alisa Yurovsky , Timothy Rosek
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element.
摘要翻译：用于注册IC（集成电路）的EDA（电子设计自动化）的约束的方法包括：将约束与识别IC设计中的约束的约束识别的值相关联; 将约束与约束关系的值相关联，将约束与至少一个EDA应用相关联; 在约束注册表元素中保存约束标识值和约束关系值; 以及向用户提供用于访问约束注册表元素的值的接口。

6. 发明申请

US20090113369A1 REGISTRY FOR ELECTRONIC DESIGN AUTOMATION OF INTEGRATED CIRCUITS 有权
标题翻译：集成电路电子设计自动化注册
公开(公告)号：US20090113369A1
公开(公告)日：2009-04-30
申请号：US11932062
申请日：2007-10-31
申请人： Regis Colwell , Gilles S.C. Lamant , Alisa Yurovsky , Timothy Rosek
发明人： Regis Colwell , Gilles S.C. Lamant , Alisa Yurovsky , Timothy Rosek
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for registering constraints for EDA (Electronic Design Automation) of an IC (Integrated circuit) includes: associating a constraint with values for constraint identification that identify the constraint in an IC design; associating the constraint with values for constraint relationships that relate the constraint to at least one EDA application; saving the constraint identification values and the constraint relationship values in a constraint registry element; and providing an interface to a user for accessing values of the constraint registry element.
摘要翻译：用于注册IC（集成电路）的EDA（电子设计自动化）的约束的方法包括：将约束与识别IC设计中的约束的约束识别的值相关联; 将约束与约束关系的值相关联，将约束与至少一个EDA应用相关联; 在约束注册表元素中保存约束标识值和约束关系值; 以及向用户提供用于访问约束注册表元素的值的接口。

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