专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09064063B1 Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints 有权
标题翻译：用于实现复杂约束的交互式，实时检查或验证的方法，系统和制造
公开(公告)号：US09064063B1
公开(公告)日：2015-06-23
申请号：US13445860
申请日：2012-04-12
申请人： Henry Yu , Joshua Baudhuin , Regis Colwell , Harsh Deshmane , Elias L. Fallon , Sanjib Ghosh , Anjna Khanna , Yinnie Lee , Harindranath Parameswaran , Pardeep Juneja , Roland Ruehl , Simon Simonian , Hui Xu , Timothy Rosek
发明人： Henry Yu , Joshua Baudhuin , Regis Colwell , Harsh Deshmane , Elias L. Fallon , Sanjib Ghosh , Anjna Khanna , Yinnie Lee , Harindranath Parameswaran , Pardeep Juneja , Roland Ruehl , Simon Simonian , Hui Xu , Timothy Rosek
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/06
摘要： Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.
摘要翻译：公开了包括用于实现约束的交互式检查的方法，系统，计算机程序产品。各种实施方案通过绑定器映射过程桥接原理图设计环境和布局环境，并利用原理图设计中的连接信息在物理设计阶段早期识别约束违规。该方法识别或创建布局，并识别或生成修改过程的对象。该方法可以获取设计数据库的快照，或者可以使用一个或多个日志来恢复设计数据库。该方法然后识别或创建便笺本，并对对象执行修改过程以生成更改。该方法在修改过程中使用暂存器和触发器执行约束检查，以在向持久性数据库提交更改之前提供响应于修改过程的交互式反馈。

2. 发明授权

US08694943B1 Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness 有权
标题翻译：用于实现具有连通性和约束意识的电子设计的方法，系统和计算机程序产品
公开(公告)号：US08694943B1
公开(公告)日：2014-04-08
申请号：US13445874
申请日：2012-04-12
申请人： Henry Yu , Roland Ruehl , Elias L. Fallon , Regis Colwell , Joshua Baudhuin , Hui Xu , Harsh Deshmane , Yinnie Lee , Simon Simonian , Harindranath Parameswaran , Pardeep Juneja , Anjna Khanna , Sanjib Ghosh , Timothy Rosek
发明人： Henry Yu , Roland Ruehl , Elias L. Fallon , Regis Colwell , Joshua Baudhuin , Hui Xu , Harsh Deshmane , Yinnie Lee , Simon Simonian , Harindranath Parameswaran , Pardeep Juneja , Anjna Khanna , Sanjib Ghosh , Timothy Rosek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Disclosed are methods and systems for implementing constraint and connectivity aware physical designs. The method or system provides a connectivity-aware environment to implement electronic designs. For example, the method interactively determines whether an electronic design complies with various constraints by using connectivity information in a nearly real-time manner while the electronic design is being created in some embodiments. The method or system uses the connectivity information provided by a connectivity engine or specified by designers to present feedback to a user as to whether a newly created object or a newly modified object complies or violates certain relevant constraints in an interactive manner or in nearly real-time without having to perform such constraints checking in batch mode. The method further enables one to implement electronic designs by using connectivity information without performing extraction on layouts or rebuilding nets.
摘要翻译：公开了用于实现约束和连接感知物理设计的方法和系统。该方法或系统提供了实现电子设计的连接感知环境。例如，该方法通过在一些实施例中在创建电子设计的同时以几乎实时的方式交互地确定电子设计是否符合各种约束。该方法或系统使用由连接引擎提供的或由设计者指定的连接信息，以向用户呈现关于新创建的对象或新修改的对象是否以交互方式或几乎实时的方式来遵守或违反某些相关约束的反馈，时间，而不必在批处理模式下执行这种约束检查。该方法还使得能够通过使用连接信息来实现电子设计，而不在布局或重建网络上执行提取。

3. 发明授权

US06918102B2 Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout 有权
标题翻译：用于在半导体电路布局中精确地相对定位器件的方法和装置
公开(公告)号：US06918102B2
公开(公告)日：2005-07-12
申请号：US10338311
申请日：2003-01-08
申请人： Rob A. Rutenbar , Regis R. Colwell , Elias L. Fallon
发明人： Rob A. Rutenbar , Regis R. Colwell , Elias L. Fallon
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method of determining the position of devices in a circuit layout includes defining an array of cells and defining a plurality of device outlines in the array, with each device outline received in at least one cell. A set of size constraints is established that expresses the size of each device. For each column and each row of cells having a plurality of device outlines contained completely therein, the position of one of the device outlines is determined and a constraint is established for each other device outline that expresses its position with respect to the position of the one device outline. A spacing constraint for each pair of adjacent device outlines is established that expresses a spacing therebetween. The foregoing constraints are solved simultaneously and a layout of the device outlines is generated in accordance with the solution.
摘要翻译：确定电路布局中的设备的位置的方法包括定义单元阵列并且定义阵列中的多个设备轮廓，每个设备轮廓在至少一个单元中接收。建立一组大小约束，表示每个设备的大小。对于每列具有完整包含多个器件轮廓的每个单元格的单元格行，确定其中一个器件轮廓的位置，并且为每个其他器件轮廓建立约束，该轮廓表示其相对于该位置的位置的位置设备大纲。建立每对相邻设备轮廓的间隔约束，其间表示间隔。同时解决上述约束，并根据解决方案生成设备轮廓的布局。

4. 发明授权

US06711725B1 Method of creating conformal outlines for use in transistor level semiconductor layouts 有权
标题翻译：创建用于晶体管级半导体布局的保形轮廓的方法
公开(公告)号：US06711725B1
公开(公告)日：2004-03-23
申请号：US10062121
申请日：2002-01-31
申请人： Rob A. Rutenbar , Donald B. Reaves , Elias L. Fallon
发明人： Rob A. Rutenbar , Donald B. Reaves , Elias L. Fallon
IPC分类号： G06F545
CPC分类号： G06F17/5068
摘要： A conformal outline of a well which is to receive elements of a circuit is formed from one or more candidate rectangles which enclose input rectangles. The one or more candidate rectangles are determined based upon a cost of the candidate rectangles determined therefor based on the overlap of the candidate rectangles with one or more penalty or avoid rectangles. Each input rectangle represents an area where it is desired to place elements of the circuit and each penalty or avoid rectangle represent an area where it is desired to avoid placing elements of the circuit. To determine the candidate rectangle(s) having the most advantageous cost, a side and/or an edge of each candidate rectangle is positioned at or near plural locations where the sides and/or edges of the input rectangles reside and a cost is determined therefor. The candidate rectangle(s) having the most favorable cost are then utilized as solution rectangles for the conformal outline.
摘要翻译：用于接收电路元件的阱的保形轮廓由一个或多个包围输入矩形的候选矩形形成。基于使用一个或多个惩罚或避免矩形的候选矩形的重叠，基于由其确定的候选矩形的成本来确定一个或多个候选矩形。每个输入矩形表示希望放置电路元件的区域，并且每个罚款或避免矩形表示希望避免放置电路元件的区域。为了确定具有最有利成本的候选矩形，每个候选矩形的边和/或边缘位于输入矩形的边和/或边缘所在的多个位置处或附近，并且由此确定成本。然后将具有最有利成本的候选矩形用作适形轮廓的解矩形。

5. 发明授权

US09298871B1 Method and system for implementing translations of parameterized cells 有权
标题翻译：用于实现参数化单元的翻译的方法和系统
公开(公告)号：US09298871B1
公开(公告)日：2016-03-29
申请号：US13333929
申请日：2011-12-21
申请人： Elias L. Fallon
发明人： Elias L. Fallon
IPC分类号： G06F17/50 , G06F11/36 , G06F9/45
CPC分类号： G06F17/5072 , G06F8/443 , G06F8/51 , G06F11/3664 , G06F17/505
摘要： Disclosed is a method and system for translating parameterized cells (pcells) that are created using different programming languages. The pcell source code created in a first programming language undergoes a translation process to translate that source code to a second programming language. A validation process is also provided to ensure the correctness of the translations.
摘要翻译：公开了一种用于翻译使用不同编程语言创建的参数化单元（pcell）的方法和系统。以第一编程语言创建的pcell源代码进行翻译过程，将该源代码转换为第二种编程语言。还提供了验证过程以确保翻译的正确性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式