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1. 发明授权

US08086983B2 Method and system for performing improved timing window analysis 有权
标题翻译：执行改进的时序窗口分析的方法和系统
公开(公告)号：US08086983B2
公开(公告)日：2011-12-27
申请号：US12241278
申请日：2008-09-30
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.
摘要翻译：公开了一种使用一阶参数化分析建模进行串扰分析的方法，系统和计算机程序产品。该方法可用于考虑定时窗口定义中过程变化的影响。这种方法允许人们绕过与使用定时窗口的最佳情况/最差情况分析相关的简单假设，并提供时序窗口对噪声分析的影响的真实图像。可以根据各个过程参数来查看计时窗口。过程参数可以是实际过程参数，也可以是基于实际过程参数的虚拟/计算组件。过程参数可用于计算用于执行噪声分析的定时窗口的重叠。

2. 发明申请

US20090164194A1 Netlist Partitioning for Characterizing Effect of Within-Die Variations 有权
标题翻译：用于表征内部变化影响的网表分区
公开(公告)号：US20090164194A1
公开(公告)日：2009-06-25
申请号：US11961787
申请日：2007-12-20
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.
摘要翻译：提出了用于确定过程变化对具有多个设备的集成电路的泄漏的影响的技术。使用设备的工艺参数的第一组值来模拟电路的操作，并且还利用变化的一些过程参数值来模拟电路的操作。对于具有不同值的仿真，电路被分成不同的组件（例如通道耦合组件，CCC），其中每个组件具有一个或多个设备，以及在两个或更多个设备中的每一个中的设备中的过程参数值这些组件是多样的。

3. 发明授权

US08612199B2 Netlist partitioning for characterizing effect of within-die variations 有权
标题翻译：用于表征模内变化影响的网表分区
公开(公告)号：US08612199B2
公开(公告)日：2013-12-17
申请号：US11961787
申请日：2007-12-20
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Techniques are presented for determining effects of process variations on the leakage of an integrated circuit having multiple devices. The operation of the circuit is simulated using a first set of values for the process parameters for the devices and is also simulated with some of the process parameter values varied. For the simulation with the varied values, the circuit is split up into distinct components (such as channeled coupled components, CCCs), where each component has one or more devices, and a process parameters value in a device in each of two or more of these components is varied.
摘要翻译：提出了用于确定过程变化对具有多个设备的集成电路的泄漏的影响的技术。使用设备的工艺参数的第一组值来模拟电路的操作，并且还利用变化的一些过程参数值来模拟电路的操作。对于具有不同值的仿真，电路被分成不同的组件（例如通道耦合组件，CCC），其中每个组件具有一个或多个设备，以及在两个或更多个设备中的每一个中的设备中的过程参数值这些组件是多样的。

4. 发明授权

US08813006B1 Accelerated characterization of circuits for within-die process variations 有权
标题翻译：电路内部加速表征模内工艺变化
公开(公告)号：US08813006B1
公开(公告)日：2014-08-19
申请号：US12055505
申请日：2008-03-26
申请人： Harindranath Parameswaran , Sachin Shrivastava
发明人： Harindranath Parameswaran , Sachin Shrivastava
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a netlist of a subcircuit to determine one or more input pins and one or more output pins; forming an arc graph of the subcircuit including one or more timing arcs between the one or more input pins and the one or more output pins; and reducing the number of transistors to perturb to perform a sensitivity analysis for within die process variations over the one or more timing arcs to reduce the number of simulations to characterize the subcircuit.
摘要翻译：在本发明的一个实施例中，公开了一种用于电子电路设计的方法。该方法包括分析子电路的网表以确定一个或多个输入引脚和一个或多个输出引脚; 形成所述子电路的弧形图，其包括所述一个或多个输入引脚与所述一个或多个输出引脚之间的一个或多个定时弧; 并且减少晶体管的数量以扰乱以在一个或多个定时弧上的管芯工艺变化内执行灵敏度分析，以减少用于表征子电路的仿真次数。

5. 发明申请

US20100083202A1 METHOD AND SYSTEM FOR PERFORMING IMPROVED TIMING WINDOW ANALYSIS 有权
标题翻译：用于执行改进的时序窗口分析的方法和系统
公开(公告)号：US20100083202A1
公开(公告)日：2010-04-01
申请号：US12241278
申请日：2008-09-30
申请人： Sachin Shrivastava , Harindranath Parameswaran
发明人： Sachin Shrivastava , Harindranath Parameswaran
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method, system, and computer program product are disclosed for performing crosstalk analysis using first-order parameterized analysis modeling. The approach can be used to factor in the effect of process variations within the definition of timing windows. This approach allows one to bypass the simplistic assumptions related to best-case/worst-case analysis using timing windows, and provide a realistic picture of the impact of timing windows on noise analysis. The timing windows can be viewed in terms of the individual process parameter. The process parameters could be real process parameters, or virtual/computed components based on the actual process parameters. The process parameters can be used to compute overlap of timing windows for performing noise analysis.
摘要翻译：公开了一种使用一阶参数化分析建模进行串扰分析的方法，系统和计算机程序产品。该方法可用于考虑定时窗口定义中过程变化的影响。这种方法允许人们绕过与使用定时窗口的最佳情况/最差情况分析相关的简单假设，并提供时序窗口对噪声分析的影响的真实图像。可以根据各个过程参数来查看计时窗口。过程参数可以是实际过程参数，也可以是基于实际过程参数的虚拟/计算组件。过程参数可用于计算用于执行噪声分析的定时窗口的重叠。

6. 发明授权

US08336010B1 Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits 有权
标题翻译：针对集成电路静态时序分析的芯片变化降额因子设计专用
公开(公告)号：US08336010B1
公开(公告)日：2012-12-18
申请号：US12824191
申请日：2010-06-27
申请人： Hongliang Chang , Vassilios Gerousis , Sireesha Molakalapalli , Sachin Shrivastava
发明人： Hongliang Chang , Vassilios Gerousis , Sireesha Molakalapalli , Sachin Shrivastava
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.
摘要翻译：在本发明的一个实施例中，公开了一种分析关于管芯内工艺变化的电路设计的方法，以产生设计专用的片上变化（DS-OCV）降额因子。该方法包括使用过程角库在片上变化模式下执行静态时序分析（STA）。收集前N个关键时序路径的定时信息。在N个关键定时路径上执行统计静态时序分析（SSTA），其使用以SSTA为特征的定时模型，具有对过程变量的延迟敏感性。比较两个定时结果，并得出要在STA OCV时序分析中使用的时钟/数据路径的DS-OCV降额因子，以正确说明过程变化的影响。用户可以选择为路径或路径组指定DS-OCV降额因子，并以减少的运行时间量来实现准确的时序分析报告。

7. 发明授权

US08086978B2 Method and system for performing statistical leakage characterization, analysis, and modeling 有权
标题翻译：执行统计泄漏表征，分析和建模的方法和系统
公开(公告)号：US08086978B2
公开(公告)日：2011-12-27
申请号：US12143547
申请日：2008-06-20
申请人： Lizheng Zhang , Parveen Khurana , Vassilios Gerousis , Hongliang Chang , Sachin Shrivastava
发明人： Lizheng Zhang , Parveen Khurana , Vassilios Gerousis , Hongliang Chang , Sachin Shrivastava
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10 , G06F2217/78
摘要： A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于执行统计泄漏功率表征以估计电路在泄漏功率方面的产量。根据一些方法，这是考虑到状态相关性来进行的。

8. 发明授权

US08762908B1 Static timing analysis with design-specific on chip variation de-rating factors 有权
标题翻译：静态时序分析与设计特定的片上变化降额因素
公开(公告)号：US08762908B1
公开(公告)日：2014-06-24
申请号：US12824194
申请日：2010-06-27
申请人： Hongliang Chang , Vassilios Gerousis , Sireesha Molakalapalli , Sachin Shrivastava
发明人： Hongliang Chang , Vassilios Gerousis , Sireesha Molakalapalli , Sachin Shrivastava
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time.
摘要翻译：在本发明的一个实施例中，公开了一种分析关于管芯内工艺变化的电路设计的方法，以产生设计专用的片上变化（DS-OCV）降额因子。该方法包括使用过程角库在片上变化模式下执行静态时序分析（STA）。收集前N个关键时序路径的定时信息。在N个关键定时路径上执行统计静态时序分析（SSTA），其使用以SSTA为特征的定时模型，具有对过程变量的延迟敏感性。比较两个定时结果，并得出要在STA OCV时序分析中使用的时钟/数据路径的DS-OCV降额因子，以正确说明过程变化的影响。用户可以选择为路径或路径组指定DS-OCV降额因子，并以减少的运行时间量来实现准确的时序分析报告。

9. 发明申请

US20090319969A1 METHOD AND SYSTEM FOR PERFORMING STATISTICAL LEAKAGE CHARACTERIZATION, ANALYSIS, AND MODELING 有权
标题翻译：执行统计泄漏特征，分析和建模的方法和系统
公开(公告)号：US20090319969A1
公开(公告)日：2009-12-24
申请号：US12143547
申请日：2008-06-20
申请人： Lizheng Zhang , Parveen Khurana , Vassilios Gerousis , Hongliang Chang , Sachin Shrivastava
发明人： Lizheng Zhang , Parveen Khurana , Vassilios Gerousis , Hongliang Chang , Sachin Shrivastava
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10 , G06F2217/78
摘要： A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于执行统计泄漏功率表征以估计电路在泄漏功率方面的产量。根据一些方法，这是考虑状态相关性来进行的。

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