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1. 发明授权

US07292065B2 Enhanced passgate structures for reducing leakage current 有权
标题翻译：增强型门窗结构，减少漏电流
公开(公告)号：US07292065B2
公开(公告)日：2007-11-06
申请号：US10910891
申请日：2004-08-03
申请人： Henry Y. Lui , Malik Kabani , Rakesh Patel , Tim Tri Hoang
发明人： Henry Y. Lui , Malik Kabani , Rakesh Patel , Tim Tri Hoang
IPC分类号： H03K19/173
CPC分类号： H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.
摘要翻译：提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。

2. 发明授权

US07046174B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US07046174B1
公开(公告)日：2006-05-16
申请号：US11147757
申请日：2005-06-07
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135 , H04L7/0331
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

3. 发明授权

US06724328B1 Byte alignment for serial data receiver 有权
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06724328B1
公开(公告)日：2004-04-20
申请号：US10454626
申请日：2003-06-03
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M900
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

4. 发明授权

US06970117B1 Byte alignment for serial data receiver 失效
标题翻译：串行数据接收器的字节对齐
公开(公告)号：US06970117B1
公开(公告)日：2005-11-29
申请号：US10789406
申请日：2004-02-26
申请人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
发明人： Henry Y. Lui , Chong H. Lee , Rakesh Patel , Ramanand Venkata , John Lam , Vinson Chan , Malik Kabani
IPC分类号： H03M9/00 , H04L7/02
CPC分类号： H04L7/0054 , H03M9/00
摘要： A serial data interface for a programmable logic device includes a receiver that deserializes a plurality of channels of received serial data using a recovered clock signal or a phase-aligned received clock signal. Byte boundaries are initially assigned, perhaps arbitrarily, and the deserialized signal is sent to the programmable logic core of the programmable logic device. Programmable logic in the core monitors the byte boundaries on each channel based on the criteria, including any user-defined parameters, programmed into the logic. If a boundary misalignment is detected, a signal is send from the core to bit-slipping circuitry on that channel of the interface to adjust the boundary. The signal could instruct the bit-slipping circuitry to adjust the boundary by the number of bits needed to correct the alignment. Alternatively, the bit-slipping circuitry could operate iteratively, adjusting the boundary by one bit, each cycle, until the signal stops indicating misalignment.
摘要翻译：用于可编程逻辑器件的串行数据接口包括使用恢复的时钟信号或相位对准的接收时钟信号对接收的串行数据的多个信道反串行的接收器。字节边界最初可以任意分配，反序列化信号被发送到可编程逻辑器件的可编程逻辑核心。内核中的可编程逻辑基于标准（包括任何用户定义的参数）来监视每个通道上的字节边界，编程到逻辑中。如果检测到边界未对准，则在该接口的该通道上将信号从核心发送到位滑动电路以调整边界。信号可以指示位滑动电路将边界调整校正对准所需的位数。或者，位打滑电路可以迭代地操作，每个周期将边界调整一个位，直到信号停止指示未对准。

5. 发明授权

US07639993B1 Power supply circuitry for data signal transceivers on integrated circuits 有权
标题翻译：集成电路上数据信号收发器的电源电路
公开(公告)号：US07639993B1
公开(公告)日：2009-12-29
申请号：US11295391
申请日：2005-12-05
申请人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
发明人： Sergey Yuryevich Shumarayev , Rakesh Patel , William Bereza , Wilson Wong , Tim Tri Hoang
IPC分类号： H04B1/04
CPC分类号： H04L7/033
摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.
摘要翻译：集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

6. 发明授权

US08416845B1 Decision feedback equalization for variable input amplitude 有权
标题翻译：用于可变输入幅度的判决反馈均衡
公开(公告)号：US08416845B1
公开(公告)日：2013-04-09
申请号：US11484285
申请日：2006-07-11
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Rakesh Patel , Tim Tri Hoang
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H03K5/1532
摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.
摘要翻译：提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。抽头系数可以由均衡电路自动调整。

7. 发明授权

US08189729B2 Wide range and dynamically reconfigurable clock data recovery architecture 有权
标题翻译：宽范围和动态可重构的时钟数据恢复架构
公开(公告)号：US08189729B2
公开(公告)日：2012-05-29
申请号：US11329197
申请日：2006-01-09
申请人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
发明人： Tim Tri Hoang , Sergey Yuryevich Shumarayev , Wilson Wong , Rakesh Patel
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H03K19/17732 , H03K19/17744 , H03L7/10 , H04L7/0004 , H04L7/033
摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.
摘要翻译：宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。为了支持广泛的数据速率，CDR架构包括多个操作参数。这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。可以在不关闭电路或PLD的情况下动态重新编程参数。这允许CDR电路在各种标准和协议之间进行即时切换。

8. 发明申请

US20060028240A1 ENHANCED PASSGATE STRUCTURES FOR REDUCING LEAKAGE CURRENT 有权
标题翻译：用于降低泄漏电流的增强通孔结构
公开(公告)号：US20060028240A1
公开(公告)日：2006-02-09
申请号：US10910891
申请日：2004-08-03
申请人： Henry Lui , Malik Kabani , Rakesh Patel , Tim Hoang
发明人： Henry Lui , Malik Kabani , Rakesh Patel , Tim Hoang
IPC分类号： H03K19/173
CPC分类号： H03K19/1778 , H03K19/17784 , H03K19/17792
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the operational speed of the passgate structures is maximized, while minimizing leakage current when the structure is turned “OFF.” In one arrangement, the VT of the pass-gate structures is increased relative to the VT of other transistors fabricated according to a particular process dimension. In addition, a passgate activation voltage is applied to the passgate structures such that the passgate activation voltage is higher in voltage than a nominal voltage being supplied to circuitry other than the passgate structures.
摘要翻译：提出了在低压系统中使用的增强型门控结构，其中通道结构的操作速度最大化，同时使结构“OFF”时的漏电流最小化。在一种布置中，栅极结构的栅极相对于根据特定工艺尺寸制造的其它晶体管的V IN T T T T增加。此外，通道激活电压被施加到通道结构，使得通电门激活电压的电压高于提供给非门电路结构以外的电路的标称电压。

9. 发明授权

US10078695B2 Methods and systems for network based video clip generation and management 有权
公开(公告)号：US10078695B2
公开(公告)日：2018-09-18
申请号：US13444630
申请日：2012-04-11
申请人： Vincent Silvestri , Rakesh Patel
发明人： Vincent Silvestri , Rakesh Patel
IPC分类号： G06F17/30 , H04L29/06
CPC分类号： H04N21/231 , G06F16/78 , G06F16/951 , H04L65/4076 , H04L65/4084 , H04L65/604 , H04N21/278
摘要： Methods and system for managing media clips over a data network. Media streams may be received over a data network and stored by a storage server. Metadata regarding the media streams may be generated and stored at a metadata server. A control station can retrieve media frames originating in the stored media streams from the storage server, based on metadata. Media frames from multiple media streams can be retrieved and displayed in synchronization, based on respective timecodes.

10. 发明授权

US09131213B2 Method of generating a blockiness indicator for a video signal 有权
标题翻译：产生视频信号的块效应指示符的方法
公开(公告)号：US09131213B2
公开(公告)日：2015-09-08
申请号：US12203433
申请日：2008-09-03
申请人： Jeff Wei , Rakesh Patel
发明人： Jeff Wei , Rakesh Patel
IPC分类号： H04N7/26 , H04N17/00 , H04N19/86 , H04N19/17 , H04N19/82
CPC分类号： H04N19/176 , H04N7/0155 , H04N17/004 , H04N19/167 , H04N19/17 , H04N19/182 , H04N19/66 , H04N19/82 , H04N19/86 , H04N19/865 , H04N19/88
摘要： The described embodiments relate to methods and systems for detecting the blockiness of a video signal comprised of a number of pixels. The method includes the steps of calculating a total number of pixels in the video signal in flat blocks and visible block edge transitions, and generating a blockiness indicator from the total number of pixels in flat blocks and visible block edge transitions. The step of calculating the total number of pixels in flat blocks and the total number of pixels in visible block edge transitions may include calculating differential values for each pixel in the video signal, analyzing the differential values to determine if the pixel is part of a transition and/or a flat area and then counting the number of pixels in flat blocks and visible block edge transitions to produce a total number of pixels in flat blocks and a total number of pixels in visible block edge transitions.
摘要翻译：所描述的实施例涉及用于检测包括多个像素的视频信号的块效应的方法和系统。该方法包括以下步骤：在平面块和可见块边缘转换中计算视频信号中的像素总数，并从平面块和可见块边缘转换中的像素总数生成块状指示符。计算平面块中的像素总数和可见块边缘转换中的像素总数的步骤可以包括计算视频信号中每个像素的差分值，分析差分值以确定像素是否是转变的一部分和/或平坦区域，然后对平坦块和可见块边缘过渡中的像素数进行计数，以产生平坦块中的像素总数和可见块边缘转换中的像素总数。

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