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1. 发明授权

US6144076A Well formation For CMOS devices integrated circuit structures 有权
标题翻译：形成CMOS器件集成电路结构
公开(公告)号：US6144076A
公开(公告)日：2000-11-07
申请号：US207395
申请日：1998-12-08
申请人： Helmut Puchner , Shih-Fen Huang , Ruggero Castagnetti
发明人： Helmut Puchner , Shih-Fen Huang , Ruggero Castagnetti
IPC分类号： H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/76
CPC分类号： H01L21/823892 , H01L21/76237 , H01L27/0921
摘要： A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region. The dopant concentration level peak of the dopants forming the buried P well in the substrate will be located below the dopant concentration level peak of the N well a minimum distance sufficient to inhibit reduction of the effective depth of the N well, and a maximum distance not exceeding the maximum distance which will still provide enhanced latchup protection to one or more transistors formed in the CMOS region.
摘要翻译：在半导体衬底的CMOS区域中提供多阱形成，以为形成在阱中的一个或多个CMOS晶体管提供增强的闭锁保护。该结构包括从衬底表面向下延伸到衬底中的N阱，在N阱下方的衬底中形成的掩埋P阱，从衬底表面向下延伸到衬底中的第二P阱以及形成在衬底中的隔离区 N阱和第二P阱之间的衬底。掩埋的P阱可以在衬底中的N阱和第二P阱的下方延伸。在本发明的一个优选实施方案中，N阱和第二P阱各自以足以在衬底中的掺杂剂浓度峰值（在低于隔离区域的深度）提供掺杂剂浓度峰值的能级注入到衬底中，以提供穿通保护，并且通过在隔离区之下的N阱和P阱之间提供PN结，在隔离区之下提供通道停止。在衬底中形成掩埋P阱的掺杂剂的掺杂剂浓度水平峰值将位于N阱的掺杂剂浓度水平峰值以下，其最小距离足以抑制N阱的有效深度的减小，并且最大距离不超过仍将为在CMOS区域中形成的一个或多个晶体管提供增强的闭锁保护的最大距离。

2. 发明授权

US06472715B1 Reduced soft error rate (SER) construction for integrated circuit structures 有权
标题翻译：降低集成电路结构的软错误率（SER）结构
公开(公告)号：US06472715B1
公开(公告)日：2002-10-29
申请号：US09675109
申请日：2000-09-28
申请人： Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
发明人： Yauh-Ching Liu , Helmut Puchner , Ruggero Castagnetti , Weiran Kong , Lee Phan , Franklin Duan , Steven Michael Peterson
IPC分类号： H01L2976
CPC分类号： H01L21/823892 , H01L27/11
摘要： An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the deep N well to broaden at its base. Such a broadened base deep N well will have enhanced opportunity to collect electrons generated by the alpha particle collision with the substrate. This deep N well with a broadened base can be formed either by increasing the implant energy or by tilting the substrate with respect to the axis of the implant beam while implanting the substrate to form the deep N well.
摘要翻译：诸如SRAM结构的集成电路结构，其中软错误率被降低包括形成在半导体衬底中的集成电路结构，其中至少一个N沟道晶体管被构建在邻近一个或多个深N阱的P阱中，高压电源和深N阱从衬底的表面向下延伸到衬底中的至少等于α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软错误的深度的深度。对于具有一个或多个常规深度不超过约0.5μm的N个阱的0.25μmSRAM设计，α粒子产生的电子 - 空穴对可以有效地引起SRAM单元中的软误差的深度为1至3μm 。因此，0.25μmSRAM设计的深N阱从衬底表面向下延伸至少约1um，优选至少约2μm的距离。在优选实施例中，衬底的注入以形成本发明的改进的SRAM的深N阱以将导致分段的方式进行，即，使得包括深N阱的掺杂体积在其基极处变宽。这样扩大的基底深N阱将增加收集由α粒子与基底碰撞产生的电子的机会。可以通过增加植入能量或通过相对于植入物束的轴线倾斜衬底同时植入衬底以形成深N阱来形成具有加宽基底的该深N阱。

3. 发明授权

US08411399B2 Defectivity-immune technique of implementing MIM-based decoupling capacitors 有权
标题翻译：实现基于MIM的去耦电容器的缺陷免疫技术
公开(公告)号：US08411399B2
公开(公告)日：2013-04-02
申请号：US12839148
申请日：2010-07-19
申请人： Ramnath Venkatraman , Ruggero Castagnetti
发明人： Ramnath Venkatraman , Ruggero Castagnetti
IPC分类号： H02H3/22
CPC分类号： H01L27/0629 , H01L27/0805 , H03H7/004 , Y10T29/413
摘要： An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.
摘要翻译：集成电路电源去耦电路包括电容器和保护电路。电容器具有第一端子和第二端子。保护电路包括具有第一导电路径的第一晶体管和具有第二导电路径的第二晶体管。第一导电路径的一个端子连接到电容器的第一端子，并且第一导电路径的另一个端子连接到第一电源轨道。第二导电路径的一个端子连接到电容器的第二端子，第二导电路径的另一个端子连接到第二电源轨道。

4. 发明申请

US20130057338A1 POWER CONTROLLER FOR SOC POWER GATING APPLICATIONS 有权
标题翻译：电源控制器用于SOC功率增益应用
公开(公告)号：US20130057338A1
公开(公告)日：2013-03-07
申请号：US13226038
申请日：2011-09-06
申请人： Ramnath Venkatraman , Shashidhara S. Bapat , Ruggero Castagnetti
发明人： Ramnath Venkatraman , Shashidhara S. Bapat , Ruggero Castagnetti
IPC分类号： H01L25/065
CPC分类号： H03K19/0016
摘要： A rush-in current controller includes a clock module connected to provide a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal. Additionally, the rush-in current controller includes a ring oscillator module connected to maintain the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage. A method of controlling a rush-in current includes providing a delayed sleep control signal based on counting a preset number of clock cycles corresponding to an input sleep control signal and maintaining the delayed sleep control signal based on counting a preset number of ring oscillator cycles corresponding to a virtual power supply line voltage.
摘要翻译：冲击电流控制器包括连接的时钟模块，以基于对与输入的睡眠控制信号相对应的预设数量的时钟周期计数来提供延迟的睡眠控制信号。此外，引入电流控制器包括环形振荡器模块，其连接以基于对应于虚拟电源线电压的预设数量的环形振荡器周期来计数延迟的睡眠控制信号。一种控制加速电流的方法包括：基于对与输入的睡眠控制信号相对应的预设数量的时钟周期进行计数，提供延迟睡眠控制信号，并且基于对预定数量的环形振荡器周期进行计数来保持延迟的睡眠控制信号到虚拟电源线电压。

5. 发明申请

US20120290994A1 TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT 失效
标题翻译：逻辑集成电路的总功率优化
公开(公告)号：US20120290994A1
公开(公告)日：2012-11-15
申请号：US13103461
申请日：2011-05-09
申请人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
发明人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/505 , G06F2217/78
摘要： A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided.
摘要翻译：减少逻辑单元的总功耗的方法包括：选择对应于至少一个路径的逻辑单元的分布，在逻辑单元的分布中计算每个逻辑单元的动态到静态功率比，并将动态到静态功率比排列每个逻辑单元分成下组，中间组和上组逻辑单元。此外，该方法包括交换逻辑单元的下组和用于重构的中间组逻辑单元的逻辑单元的上组，并验证重构的中间组逻辑单元的路径定时。还提供了使用布尔方程和逻辑单元组来降低总功耗的方法。

6. 发明申请

US20110051304A1 DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING CAPACITORS 有权
标题翻译：实现基于MIM的解耦电容器的缺陷免疫技术
公开(公告)号：US20110051304A1
公开(公告)日：2011-03-03
申请号：US12839148
申请日：2010-07-19
申请人： Ramnath Venkatraman , Ruggero Castagnetti
发明人： Ramnath Venkatraman , Ruggero Castagnetti
IPC分类号： H02H9/02 , H03H7/00 , H01L21/00
CPC分类号： H01L27/0629 , H01L27/0805 , H03H7/004 , Y10T29/413
摘要： An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One terminal of the second conduction path is connected to the second terminal of the capacitor, and another terminal of the second conduction path is connected to a second power supply rail.
摘要翻译：集成电路电源去耦电路包括电容器和保护电路。电容器具有第一端子和第二端子。保护电路包括具有第一导电路径的第一晶体管和具有第二导电路径的第二晶体管。第一导电路径的一个端子连接到电容器的第一端子，并且第一导电路径的另一个端子连接到第一电源轨道。第二导电路径的一个端子连接到电容器的第二端子，第二导电路径的另一个端子连接到第二电源轨道。

7. 发明申请

US20050047238A1 Reconfigurable memory arrays 有权
公开(公告)号：US20050047238A1
公开(公告)日：2005-03-03
申请号：US10655053
申请日：2003-09-03
申请人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
发明人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
IPC分类号： G11C5/02 , G11C7/02 , H01L27/02 , H01L27/105
CPC分类号： G11C5/025 , H01L27/0203 , H01L27/105
摘要： A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.

8. 发明授权

US06806551B2 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06806551B2
公开(公告)日：2004-10-19
申请号：US10376401
申请日：2003-02-28
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

9. 发明授权

US06687114B1 High density memory with storage capacitor 有权
标题翻译：具有存储电容器的高密度存储器
公开(公告)号：US06687114B1
公开(公告)日：2004-02-03
申请号：US10403433
申请日：2003-03-31
申请人： Arvind Kamath , Ruggero Castagnetti
发明人： Arvind Kamath , Ruggero Castagnetti
IPC分类号： H01G4228
CPC分类号： H01L27/1087 , H01L27/10894 , H01L29/66181
摘要： A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate. A transistor is formed having source and drain regions separated by a channel region, and a gate dielectric layer formed of the first deposited dielectric layer.
摘要翻译：具有在硅衬底中形成的晶体管和电容器的存储单元。电容器形成有在硅衬底的投影表面区域中蚀刻的下导电板。下导电板具有至少一个vee形状的横截面，其中，vee的侧面与硅衬底的顶表面成约五十五度的角度。下导电板的表面积比其中蚀刻下导电板的硅衬底的投影表面积大约百分之七点三。电容器介电层由邻近下导电板设置的第一沉积介电层形成。顶部导电板设置在电容器电介质层附近并与下部导电板相对。晶体管形成为具有由沟道区域分离的源极和漏极区域以及由第一沉积介电层形成的栅极电介质层。

10. 发明授权

US06566171B1 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06566171B1
公开(公告)日：2003-05-20
申请号：US09882404
申请日：2001-06-12
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

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