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1. 发明授权

US07869251B2 SRAM based one-time-programmable memory 有权
标题翻译：基于SRAM的一次可编程存储器
公开(公告)号：US07869251B2
公开(公告)日：2011-01-11
申请号：US12239469
申请日：2008-09-26
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.
摘要翻译：公开了一种用于提供基于SRAM存储器技术的快速响应一次可编程（OTP）存储器和MOS晶体管的固有击穿特性的方法和装置。 SRAM存储单元电路的每个存储单元连接到编程电路。编程电路由连接到SRAM存储器电路的两个交叉耦合反相器的存储节点（SN和SNB，其中SNB是SN的互补值）的两组MOS晶体管组成。将期望的数据组加载到电路中，然后通过施加并重复地循环编程电路的MOS晶体管的源极和漏极上的“老化”电压并接近特性的ON状态触发电压而被烧录双极结晶体管包含在MOS晶体管内。在重复循环源极至漏极电压之后，编程电路内的目标MOS晶体管在晶体管的栅极，漏极和/或源极之间分解和短路。当系统恢复正常运行时，编程电路将连接到地，Vdd或Vss，SRAM单元电路的两个节点之一将通过编程电路短路到地Vdd或Vss，从而强制保留编程数据状态。

2. 发明授权

US07440356B2 Modular design of multiport memory bitcells 有权
标题翻译：多端口存储器单元的模块化设计
公开(公告)号：US07440356B2
公开(公告)日：2008-10-21
申请号：US11487061
申请日：2006-07-13
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C8/00
CPC分类号： H01L27/11 , G11C8/16 , G11C11/412 , H01L27/1104
摘要： The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.
摘要翻译：本发明提供一种用于设计和模块化扩展多端口比特单元的系统和方法。描述了一种模块化设计方法，它降低了设计多端口位单元的复杂性，同时遵循了各种半导体制造提供商的DFM规则。模块化设计可以被解析成诸如读端口模块，写端口模块和可以容易地互连以构建多端口位单元的上拉模块的模块。这些模块还可以独立地定尺寸和组装以实现期望的读取边缘，写入边距，静态噪声容限以及读取访问时间和写入时间。

3. 发明申请

US20080013383A1 Modular design of multiport memory bitcells 有权
公开(公告)号：US20080013383A1
公开(公告)日：2008-01-17
申请号：US11487061
申请日：2006-07-13
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C7/10
CPC分类号： H01L27/11 , G11C8/16 , G11C11/412 , H01L27/1104
摘要： The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.

4. 发明授权

US07006370B1 Memory cell architecture 失效
标题翻译：存储单元架构
公开(公告)号：US07006370B1
公开(公告)日：2006-02-28
申请号：US10716259
申请日：2003-11-18
申请人： Subramanian Ramesh , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Subramanian Ramesh , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , H01L27/1104
摘要： A memory cell architecture is provided herein for increasing memory speed, performance and robustness within a highly compact memory cell layout. Though only a few embodiments are provided herein, a feature common to all embodiments includes a novel means for sharing one or more contact structures between vertically adjacent memory cells. In particular, one or more contact structures may be shared unequally between two vertically adjacent memory cells for reducing a vertical dimension, or length, of the memory cell. Other features are disclosed for producing the highly compact memory cell layout. The various features of the present invention may be combined to produce high-performance, high-density memory arrays.
摘要翻译：本文提供了一种存储单元架构，用于在高度紧凑的存储器单元布局内提高存储器速度，性能和鲁棒性。虽然本文仅提供了几个实施例，但是所有实施例共同的特征包括用于在垂直相邻的存储器单元之间共享一个或多个接触结构的新型装置。特别地，一个或多个接触结构可以在两个垂直相邻的存储器单元之间被不平等地共享，以减小存储单元的垂直尺寸或长度。公开了用于产生高度紧凑的存储单元布局的其它特征。本发明的各种特征可以组合以产生高性能，高密度的存储阵列。

5. 发明授权

US06934174B2 Reconfigurable memory arrays 有权
标题翻译：可重构内存阵列
公开(公告)号：US06934174B2
公开(公告)日：2005-08-23
申请号：US10655053
申请日：2003-09-03
申请人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
发明人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
IPC分类号： G11C5/02 , G11C7/02 , H01L27/02 , H01L27/105
CPC分类号： G11C5/025 , H01L27/0203 , H01L27/105
摘要： A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.
摘要翻译：公开了一种用于重配置存储器阵列的方法和系统。最初，存储器阵列中的单元以与预定义的层基本上相同的结构进行构图。此后，通过对预定层上的单元进行图案化，使得第一多个单元用作存储单元，并且第二多个单元被图案化为用作存储器阵列的断点的虚拟行或列，来重构存储器阵列。

6. 发明申请

US20100080035A1 SRAM BASED ONE-TIME-PROGRAMMABLE MEMORY 有权
标题翻译：基于SRAM的一次可编程存储器
公开(公告)号：US20100080035A1
公开(公告)日：2010-04-01
申请号：US12239469
申请日：2008-09-26
申请人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
发明人： Ramnath Venkatraman , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： G11C17/08
CPC分类号： G11C17/16 , G11C17/18
摘要： Disclosed is a method and device for providing fast-response One-Time-Programmable (OTP) memory based on SRAM memory technology and the inherent breakdown characteristics of a MOS transistor. Each memory cell of an SRAM memory cell circuit is connected to a programming circuit. The programming circuit is comprised of two groups of MOS transistors connected to the storage nodes (SN and SNB, where SNB is the complementary value of SN) of the two cross-coupled inverters of the SRAM memory circuit. A desired data set is loaded into the circuit and then is burned-in by applying and repeatedly cycling a “burn-in” voltage across the source and drain of the MOS transistors of the programming circuit that approaches the ON STATE trigger voltage of the characteristic bipolar junction transistor contained within the MOS transistors. Upon repeated cycling of the source-to-drain voltage, the targeted MOS transistor within the programming circuit breaks down and shorts across the gate, drain, and/or source of the transistor. When the system is returned to normal operation, the programming circuits will be connected to ground, Vdd or Vss and one of the two nodes of the SRAM cell circuit will be shorted through the programming circuit to ground, Vdd or Vss, thus, forcing a retention of the programmed data state.
摘要翻译：公开了一种用于提供基于SRAM存储器技术的快速响应一次可编程（OTP）存储器和MOS晶体管的固有击穿特性的方法和装置。 SRAM存储单元电路的每个存储单元连接到编程电路。编程电路由连接到SRAM存储器电路的两个交叉耦合反相器的存储节点（SN和SNB，其中SNB是SN的互补值）的两组MOS晶体管组成。将期望的数据组加载到电路中，然后通过施加并重复地循环编程电路的MOS晶体管的源极和漏极上的“老化”电压并接近特性的ON状态触发电压而被烧录双极结晶体管包含在MOS晶体管内。在重复循环源极至漏极电压之后，编程电路内的目标MOS晶体管在晶体管的栅极，漏极和/或源极之间分解和短路。当系统恢复正常运行时，编程电路将连接到地，Vdd或Vss，SRAM单元电路的两个节点之一将通过编程电路短路到地Vdd或Vss，从而强制保留编程数据状态。

7. 发明申请

US20050047238A1 Reconfigurable memory arrays 有权
公开(公告)号：US20050047238A1
公开(公告)日：2005-03-03
申请号：US10655053
申请日：2003-09-03
申请人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
发明人： Ruggero Castagnetti , Ramnath Venkatraman , Subramanian Ramesh
IPC分类号： G11C5/02 , G11C7/02 , H01L27/02 , H01L27/105
CPC分类号： G11C5/025 , H01L27/0203 , H01L27/105
摘要： A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.

8. 发明授权

US06980462B1 Memory cell architecture for reduced routing congestion 有权
标题翻译：用于减少路由拥塞的存储单元架构
公开(公告)号：US06980462B1
公开(公告)日：2005-12-27
申请号：US10715929
申请日：2003-11-18
申请人： Subramanian Ramesh , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Subramanian Ramesh , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： G11C5/06 , G11C11/00 , H01L27/02 , H01L27/105 , H01L27/118
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/11807
摘要： An improved memory cell architecture is provided herein for reducing, or altogether eliminating, chip-level routing congestion in System-on-Chip environments. Though only a few embodiments are provided herein, features common to the described embodiments include: the formation of bitlines in a lower-level metallization layer of the memory array, and the use of word lines and ground supply lines, both formed in inter-level metallization layer(s) of the memory array, for effective shielding of the bitlines against routing signals in the chip-level routing layer.
摘要翻译：本文提供了一种改进的存储单元体系结构，用于减少或完全消除片上系统片上环境中的芯片级路由拥塞。尽管本文仅提供了几个实施例，但是所描述的实施例共同的特征包括：在存储器阵列的较低级金属化层中形成位线，以及使用字线和地电源线，两者都形成在层间存储器阵列的金属化层，用于有效屏蔽位线以防止芯片级布线层中的路由信号。

9. 发明申请

US20130166931A1 REDUCING POWER CONSUMPTION OF MEMORY 审中-公开
标题翻译：降低存储器的功耗
公开(公告)号：US20130166931A1
公开(公告)日：2013-06-27
申请号：US13336826
申请日：2011-12-23
申请人： Ruggero Castagnetti , Ting Zhou , Ramnath Venkatraman
发明人： Ruggero Castagnetti , Ting Zhou , Ramnath Venkatraman
IPC分类号： G06F1/32
CPC分类号： G06F1/3275 , G06F13/4243 , G11C7/04 , G11C7/22 , G11C11/4074 , G11C2207/2227 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Described embodiments provide for a memory system which power-gates a memory operating at a first clock. Control logic in the memory system activates, during a rising edge of a second clock, the memory from a sleep mode. The memory is accessed. After a cycle of the first clock, the control logic asserts a power-gating signal, thereby returning the memory to the sleep mode. The frequency of the second clock is less than a frequency of the first clock.
摘要翻译：所描述的实施例提供对在第一时钟操作的存储器进行供电的存储器系统。存储器系统中的控制逻辑在第二时钟的上升沿期间将存储器从睡眠模式激活。内存被访问。在第一时钟的周期之后，控制逻辑断言电源门控信号，从而将存储器返回到睡眠模式。第二时钟的频率小于第一时钟的频率。

10. 发明授权

US08112734B2 Optimization with adaptive body biasing 有权
标题翻译：使用自适应身体偏置进行优化
公开(公告)号：US08112734B2
公开(公告)日：2012-02-07
申请号：US12240210
申请日：2008-09-29
申请人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
发明人： Benjamin Mbouombouo , Ramnath Venkatraman , Ruggero Castagnetti
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068
摘要： A method incorporating adaptive body biasing into an integrated circuit design flow includes the steps of (A) adding adaptive body biasing input/outputs (I/Os) during a bonding layout stage of the integrated circuit design flow, (B) floorplanning the integrated circuit design, (C) generating an adaptive body biasing mesh and (D) generating a layout of the integrated circuit design based upon a plurality of adaptive body biasing corners.
摘要翻译：将自适应主体偏置结合到集成电路设计流程中的方法包括以下步骤：（A）在集成电路设计流程的接合布局阶段期间增加自适应主体偏置输入/输出（I / O），（B）布局规划集成电路（C）产生自适应主体偏置网格和（D）基于多个自适应主体偏置角产生集成电路设计的布局。

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