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1. 发明授权

US06806551B2 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06806551B2
公开(公告)日：2004-10-19
申请号：US10376401
申请日：2003-02-28
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

2. 发明授权

US06566171B1 Fuse construction for integrated circuit structure having low dielectric constant dielectric material 有权
标题翻译：具有低介电常数介电材料的集成电路结构的保险丝结构
公开(公告)号：US06566171B1
公开(公告)日：2003-05-20
申请号：US09882404
申请日：2001-06-12
申请人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
发明人： Yauh-Ching Liu , Ruggero Castagnetti , Ramnath Venkatraman
IPC分类号： H01L2182
CPC分类号： H01L23/5258 , H01L23/5329 , H01L2224/05022 , H01L2924/01019
摘要： Fuses, and optionally metal pads, are formed over a layer of low k dielectric material structure having first openings lined with conductive barrier material and filled to form metal interconnects in the upper surface of the low k dielectric material. A dielectric layer is formed over the low k dielectric material and over the metal interconnects, and patterned to form second openings therein communicating with the metal interconnects. A conductive barrier layer is formed over this dielectric layer in contact with the metal interconnects, and patterned to form fuse portions between some of the metal interconnects, and a liner over one or more of the metal interconnects. A dielectric layer is then formed over the patterned conductive barrier layer to form a window above each fuse, and patterned to form openings over at least some of the conductive barrier liners filled with metal to form metal pads.
摘要翻译：保险丝和可选的金属焊盘形成在低k电介质材料结构的层上，其具有衬有导电阻挡材料的第一开口并且被填充以在低k电介质材料的上表面中形成金属互连。电介质层形成在低k电介质材料上方和金属互连之上，并被图案化以形成其中与金属互连连通的第二开口。导电阻挡层形成在与金属互连件接触的该电介质层上，并被图案化以在一些金属互连件之间形成熔丝部分，以及在一个或多个金属互连件上的衬垫。然后在图案化的导电阻挡层上方形成电介质层，以形成每个保险丝上方的窗口，并且图案化以在填充有金属的至少一些导电阻挡衬里上形成开口以形成金属焊盘。

3. 发明授权

US06442061B1 Single channel four transistor SRAM 有权
标题翻译：单通道四晶体管SRAM
公开(公告)号：US06442061B1
公开(公告)日：2002-08-27
申请号：US09783653
申请日：2001-02-14
申请人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
发明人： Weiran Kong , Gary K. Giust , Ramnath Venkatraman , Yauh-Ching Liu , Franklin Duan , Ruggero Castagnetti , Steven M. Peterson , Myron J. Buer , Minh Tien Nguyen
IPC分类号： G11C1100
CPC分类号： G11C11/412 , H01L27/11
摘要： A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type. The first state node transistor has a gate oxide with a second thickness. The source of the first state node transistor is electrically connected to the first state node, and the drain of the first state node transistor is electrically connected to a ground line. The gate of the first state node is electrically connected to the second state node. A second state node transistor is also formed of the first transistor type. The second state node transistor also has a gate oxide with the second thickness. The source of the second state node transistor is electrically connected to the second state node, and the drain of the second state node transistor is electrically connected to the ground line. The gate of the second state node is electrically connected to the first state node.
摘要翻译：根据本发明的形成存储单元的方法。第一栅极晶体管由第一晶体管形成。第一栅极晶体管具有第一厚度的栅极氧化物。第一栅极晶体管的源极电连接到第一位线，并且第一栅极晶体管的漏极电连接到第一状态节点。第一栅极晶体管的栅极电连接到存储器单元使能线。第二栅极晶体管也由第一晶体管形成。第二栅极晶体管还具有第一厚度的栅极氧化物。第二栅极晶体管的源极电连接到第二位线，并且第二栅极晶体管的漏极电连接到第二状态节点。第二通栅晶体管的栅极电连接到存储单元使能线。第一状态节点晶体管也由第一晶体管类型形成。第一状态节点晶体管具有第二厚度的栅极氧化物。第一状态节点晶体管的源极电连接到第一状态节点，并且第一状态节点晶体管的漏极电连接到接地线。第一状态节点的门电连接到第二状态节点。第二状态节点晶体管也由第一晶体管类型形成。第二状态节点晶体管也具有第二厚度的栅极氧化物。第二状态节点晶体管的源极电连接到第二状态节点，并且第二状态节点晶体管的漏极电连接到接地线。第二状态节点的门电连接到第一状态节点。

4. 发明授权

US06566730B1 Laser-breakable fuse link with alignment and break point promotion structures 有权
公开(公告)号：US06566730B1
公开(公告)日：2003-05-20
申请号：US09723476
申请日：2000-11-27
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.

5. 发明授权

US06218276B1 Silicide encapsulation of polysilicon gate and interconnect 失效
标题翻译：多晶硅栅极和互连的硅化物封装
公开(公告)号：US06218276B1
公开(公告)日：2001-04-17
申请号：US08995875
申请日：1997-12-22
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L213205
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/28518 , H01L29/66575
摘要： Provided is a method of forming a silicide layer on the top and sidewall surfaces of a polysilicon gate/interconnect in a MOS transistor and on the exposed surfaces of the source and drain regions of the transistor. Devices produced according to the present invention may have different types of silicide formed on their gate and their source/drain electrodes. The invention achieves the advantages of silicide encapsulation of a polysilicon gate in an MOS transistor while also providing silicidation of the source/drain regions of the transistor, thereby reducing electrode resistivity in the transistor and interconnect.
摘要翻译：提供了在MOS晶体管中的多晶硅栅/互连的顶壁和侧壁表面以及晶体管的源极和漏极区域的暴露表面上形成硅化物层的方法。根据本发明生产的器件可以在其栅极及其源极/漏极上形成不同类型的硅化物。本发明实现了MOS晶体管中多晶硅栅极的硅化物封装的优点，同时还提供了晶体管的源极/漏极区域的硅化，从而降低了晶体管和互连中的电极电阻率。

6. 发明授权

US6061264A Self-aligned fuse structure and method with anti-reflective coating 失效
标题翻译：自对准保险丝结构和防反射涂层方法
公开(公告)号：US6061264A
公开(公告)日：2000-05-09
申请号：US118602
申请日：1998-07-17
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： G11C17/14 , G11C11/42 , G11C13/04
CPC分类号： G11C17/14
摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithography and an anti-reflective coating. The self-alignment allows the size and location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.
摘要翻译：提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。保险丝断点，熔断器的电气连接部分被激光束切断的点，通过使用光刻和抗反射涂层进行自对准。自对准允许断点的尺寸和位置对激光束的尺寸和对准不太敏感。这具有几个优点，包括允许光刻控制和激光光斑照射熔丝材料和周围结构的有效尺寸减小。这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。此外，激光对准不太关键，因此耗时更少，这增加了制造中的吞吐量。

7. 发明授权

US6037233A Metal-encapsulated polysilicon gate and interconnect 失效
标题翻译：金属封装的多晶硅栅极和互连
公开(公告)号：US6037233A
公开(公告)日：2000-03-14
申请号：US69027
申请日：1998-04-27
申请人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
发明人： Yauh-Ching Liu , Gary K. Giust , Ruggero Castagnetti , Subramanian Ramesh
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49
CPC分类号： H01L29/66515 , H01L21/28105 , H01L29/4983 , H01L29/66575
摘要： Provided are methods of forming a metal layer on the horizontal and vertical surfaces of a polysilicon gate electrode/interconnect in a MOS transistor, and devices having metal-encapsulated gates and interconnects. The metal encapsulation method of the present invention may also provide a layer of metal on the exposed surfaces of the source and drain regions of the transistor. The methods and apparatuses of the present invention allow reductions in device resistance and signal propagation delays.
摘要翻译：提供了在MOS晶体管中的多晶硅栅电极/互连的水平和垂直表面上形成金属层的方法，以及具有金属封装的栅极和互连的器件。本发明的金属封装方法还可以在晶体管的源极和漏极区域的暴露表面上提供金属层。本发明的方法和装置允许减少器件电阻和信号传播延迟。

8. 发明授权

US06770947B2 Laser-breakable fuse link with alignment and break point promotion structures 有权
标题翻译：具有对准和断点促进结构的激光可破坏的熔断体
公开(公告)号：US06770947B2
公开(公告)日：2004-08-03
申请号：US10365240
申请日：2003-02-12
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Shiva Ramesh
IPC分类号： H01L2702
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickness of the severable portion, an elevated lower surface of the severable portion above adjoining portions of the fuse link, a protrusion which supports the severable portion at a height greater than a height of the adjoining portions of the fuse link, flowing the melted severable portion down sloped surfaces away from a break point, and a propellent material beneath the severable portion which explodes to ablate the severable portion.
摘要翻译：熔断体的可分开的水平部分相对于IC中的竖直构造的结构形成，以在从激光束施加能量时促进可分离部分的分离。竖直构造的结构可以是可分割部分的减小的垂直厚度，在熔断体的相邻部分上方的可分割部分的升高的下表面，突出部，其在大于相邻部分的高度的高度处支撑可分离部分所述熔断体将熔化的可分离部分沿着远离断裂点的倾斜表面向下流动，以及在所述可分离部分下方的推进材料，所述推进材料爆炸以消融所述可分割部分。

9. 发明授权

US06413848B1 Self-aligned fuse structure and method with dual-thickness dielectric 有权
标题翻译：自对准保险丝结构和双层电介质的方法
公开(公告)号：US06413848B1
公开(公告)日：2002-07-02
申请号：US09534907
申请日：2000-03-23
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： H01L2144
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.
摘要翻译：提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。保险丝断点，其中熔断器的电连接部分被激光束切断的点通过使用光刻图案的抗反射电介质涂层自对准。自对准允许断点的尺寸位置对激光束尺寸和对准不那么敏感。这具有几个优点，包括允许光刻控制和激光点照射熔丝材料和周围结构的有效尺寸减小。这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。此外，激光对准不太关键，因此不及时，这增加了制造的吞吐量。

10. 发明授权

US06259146B1 Self-aligned fuse structure and method with heat sink 失效
标题翻译：自对准保险丝结构及散热方式
公开(公告)号：US06259146B1
公开(公告)日：2001-07-10
申请号：US09118232
申请日：1998-07-17
申请人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
发明人： Gary K. Giust , Ruggero Castagnetti , Yauh-Ching Liu , Subramanian Ramesh
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned dielectric and a heat sink material. The self-alignment allows the size and location of the break point to be more forgiving of the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication. The present invention exploits the characteristic of most dielectric materials that they are poor conductors of thermal energy. Thermal resistance increases with the thickness of the dielectric. Thus that heat is conducted more easily and thus quickly through a relatively thin portion of dielectric than it is through a relatively thick portion of dielectric. In alternative embodiments, the present invention also exploits the characteristic of a dielectric material that its reflectance changes with its thickness due to optical interference effects. In such embodiments, the self-alignment of the fuse break point is further facilitated by the use of photolithography and anti-reflective coatings.
摘要翻译：提供了自对准的半导体熔丝结构，制造这种熔丝结构的方法，以及结合这样的熔丝结构的装置。保险丝断点，熔丝部分的电连接部分被激光束切断的点，通过使用光刻图案化电介质和散热材料自对准。自对准允许断点的尺寸和位置更宽容激光束尺寸和对准。这具有几个优点，包括允许光刻控制和激光光斑照射熔丝材料和周围结构的有效尺寸减小。这允许减小熔丝间距，增加密度和使用芯片面积的效率，并且导致减少的热暴露，这对芯片造成较小的损坏。此外，激光对准不太关键，因此耗时更少，这增加了制造中的生产量。本发明利用大多数介电材料的特性，它们是不良的热能导体。热阻随电介质的厚度而增加。因此，通过电介质的相对较薄的部分比通过电介质的相对较厚的部分，热更容易地传导并且因此被快速地传导。在替代实施例中，本发明还利用介电材料的特性，其反射率由于光学干涉效应而随其厚度而变化。在这样的实施例中，通过使用光刻和抗反射涂层进一步促进了熔断器断点的自对准。

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