专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06268640B1 Forming steep lateral doping distribution at source/drain junctions 失效
标题翻译：在源极/漏极结处形成陡峭的横向掺杂分布
公开(公告)号：US06268640B1
公开(公告)日：2001-07-31
申请号：US09373161
申请日：1999-08-12
申请人： Heemyong Park , Yuan Taur , Hsing-Jen C. Wann
发明人： Heemyong Park , Yuan Taur , Hsing-Jen C. Wann
IPC分类号： H01L2972
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/7836
摘要： A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or both.
摘要翻译：半导体器件通过将半导体衬底注入至少约10°的倾斜角度的非掺杂离子来制造，以横向延伸衬底部分的预变形，然后将其注入到用于提供源极/漏极扩展或晕圈掺杂的衬底掺杂物中，都。

2. 发明授权

US06593617B1 Field effect transistors with vertical gate side walls and method for making such transistors 失效
标题翻译：具有垂直栅极侧壁的场效应晶体管和用于制造这种晶体管的方法
公开(公告)号：US06593617B1
公开(公告)日：2003-07-15
申请号：US09026093
申请日：1998-02-19
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
IPC分类号： H01L2976
CPC分类号： H01L29/66583
摘要： Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt. Such an FET can be made using the following method: forming a dielectric stack on a semiconductor structure which at least comprises a pad oxide layer; defining an etch window having the lateral size and shape of a gate pillar to be formed; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the dielectric stack surrounding the gate hole; removing at least part of the dielectric stack such that a gate pillar with vertical side walls is set free.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域和封装沟道区域的源极区域。栅极氧化物位于通道区域上，并且具有垂直侧壁的栅极导体位于该栅极氧化物上。源极区域和沟道区域以及漏极区域和沟道区域之间的界面是突然的。可以使用以下方法制造FET：在至少包括衬垫氧化物层的半导体结构上形成电介质堆叠;限定蚀刻窗口，其具有要形成的门柱的横向尺寸和形状;通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来在电介质堆叠中限定栅极孔;沉积栅极导体，使得其填充栅极孔;去除覆盖围绕栅极孔的电介质堆叠的部分的栅极导体;去除至少部分介电堆叠，使得具有垂直侧壁的门柱被释放。

3. 发明授权

US5780327A Vertical double-gate field effect transistor 失效
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US5780327A
公开(公告)日：1998-07-14
申请号：US840741
申请日：1997-04-16
申请人： Jack Oon Chu , Louis Lu-Chen Hsu , Jack Allan Mandelman , Yuan-Chen Sun , Yuan Taur
发明人： Jack Oon Chu , Louis Lu-Chen Hsu , Jack Allan Mandelman , Yuan-Chen Sun , Yuan Taur
IPC分类号： H01L21/8238 , H01L21/336 , H01L27/092 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L29/7827 , H01L29/78612 , H01L29/78642
摘要： A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.
摘要翻译：垂直双栅极场效应晶体管包括在体或SOI衬底上排列成堆叠的源极层，外延沟道层和漏极层。栅极氧化物使用差分氧化速率在堆叠的侧面热生长以最小化输入电容问题。栅极围绕堆叠的一端缠绕，而在第二端形成触点。嵌入堆叠的第二端的蚀刻停止层使得能够直接与沟道层进行接触。

4. 发明授权

US5604368A Self-aligned double-gate MOSFET by selective lateral epitaxy 失效
标题翻译：通过选择性横向外延自对准双栅极MOSFET
公开(公告)号：US5604368A
公开(公告)日：1997-02-18
申请号：US407175
申请日：1995-03-21
申请人： Yuan Taur , Hon-Sum P. Wong
发明人： Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L27/01 , H01L27/12 , H01L29/76
CPC分类号： H01L29/66772 , H01L29/78648
摘要： A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.
摘要翻译：公开了一种制造双栅极MOSFET结构的新方法。该方法利用硅的选择性横向外延生长成形成在两个牺牲绝缘膜之间的薄间隙，用于精确的厚度控制。牺牲膜然后由栅极材料（例如，多晶硅）代替，使得顶部栅极和底部栅极彼此自对准并且与沟道区域相对。还公开了根据前述方法构造的自对准双栅极MOSFET。

5. 发明授权

US06365465B1 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06365465B1
公开(公告)日：2002-04-02
申请号：US09272297
申请日：1999-03-19
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L21336
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

6. 发明授权

US5298786A SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same 失效
标题翻译：具有边缘基底接触的SOI横向双极晶体管及其制造方法
公开(公告)号：US5298786A
公开(公告)日：1994-03-29
申请号：US93515
申请日：1993-07-19
申请人： Ghavam G. Shahidi , Denny D. Tang , Yuan Taur
发明人： Ghavam G. Shahidi , Denny D. Tang , Yuan Taur
IPC分类号： H01L21/331 , H01L21/84 , H01L29/10 , H01L29/73 , H01L29/735 , H01L29/72
CPC分类号： H01L29/6625 , H01L21/84 , H01L29/1008 , H01L29/7317 , H01L29/735
摘要： A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of the transistor. The polysilicon extrinsic base is very heavily doped and the thin oxide layer acts as both a diffusion stop and an etch stop during the formation of the extrinsic base. A silicon edge contact region is formed of selective epitaxy or polysilicon to connect the extrinsic base to the intrinsic base formed in the silicon-on-insulator layer.
摘要翻译：公开了具有边缘带状基极接触的绝缘体上的绝缘体侧面双极晶体管。在绝缘体上的结构上沉积薄层的氧化物，并且在图案化和蚀刻的薄氧化物层上沉积多晶硅层，以形成晶体管的非本征基极区域。多晶硅外部基极是非常重的掺杂，并且薄的氧化物层在形成外部基极期间充当扩散停止和蚀刻停止。硅边缘接触区域由选择性外延或多晶硅形成，以将外部基极连接到在绝缘体上硅层中形成的本征基极。

7. 发明授权

US06759710B2 Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques 失效
标题翻译：通过选择性外延和硅晶片结合技术的自对准双栅极MOSFET
公开(公告)号：US06759710B2
公开(公告)日：2004-07-06
申请号：US10051562
申请日：2002-01-18
申请人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
发明人： Kevin K. Chan , Guy M. Cohen , Yuan Taur , Hon-Sum P. Wong
IPC分类号： H01L2976
CPC分类号： H01L29/78654 , H01L21/76251 , H01L21/76264 , H01L21/76275 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/78648 , H01L29/78684 , H01L29/78687 , H01L29/78696
摘要： A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.
摘要翻译：制造双栅极金属氧化物半导体晶体管的结构和方法包括在单晶硅沟道的每一侧上形成具有单晶硅沟道层和绝缘氧化物层和氮化物层的叠层结构，在层叠结构中形成开口，在开口中形成漏极和源极区域，掺杂漏极和源极区域，在层压结构上形成掩模，去除未被掩模保护的层压结构的部分，去除掩模和绝缘氧化物和氮化物层以留下单个从漏极和源极区域悬置的晶体硅沟道层，形成覆盖漏极和源极区域和沟道层的氧化物层，以及在氧化物层上形成双栅极导体，使得双栅极导体包括第一导体在单晶硅沟道层的第一侧和在单晶的第二面上的第二导体 l硅通道层。

8. 发明授权

US5689127A Vertical double-gate field effect transistor 失效
标题翻译：垂直双栅场效应晶体管
公开(公告)号：US5689127A
公开(公告)日：1997-11-18
申请号：US610949
申请日：1996-03-05
申请人： Jack Oon Chu , Louis Lu-Chen Hsu , Jack Allan Mandelman , Yuan-Chen Sun , Yuan Taur
发明人： Jack Oon Chu , Louis Lu-Chen Hsu , Jack Allan Mandelman , Yuan-Chen Sun , Yuan Taur
IPC分类号： H01L21/8238 , H01L21/336 , H01L27/092 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94
CPC分类号： H01L29/66666 , H01L29/7827 , H01L29/78612 , H01L29/78642
摘要： A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.
摘要翻译：垂直双栅极场效应晶体管包括在体或SOI衬底上排列成堆叠的源极层，外延沟道层和漏极层。栅极氧化物使用差分氧化速率在堆叠的侧面热生长以最小化输入电容问题。栅极围绕堆叠的一端缠绕，而在第二端形成触点。嵌入堆叠的第二端的蚀刻停止层使得能够直接与沟道层进行接触。

9. 发明授权

US5541427A SRAM cell with capacitor 失效
标题翻译：带电容器的SRAM单元
公开(公告)号：US5541427A
公开(公告)日：1996-07-30
申请号：US162588
申请日：1993-12-03
申请人： Barbara A. Chappell , Bijan Davari , George A. Sai-Halasz , Yuan Taur
发明人： Barbara A. Chappell , Bijan Davari , George A. Sai-Halasz , Yuan Taur
IPC分类号： G11C11/412 , H01L27/11 , H01L27/108
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch. A six device SRAM cell comprises a deep isolation trench formed in the substrate; a first latch including two transistors formed of p-type material on a first side of the trench; a second latch including two transistors formed of n-type material on a second side of the trench opposite the first side of the trench, and connection means for electrically cross wiring the transistors of the first latch to the transistors of the second latch. In forming the latch a self-aligned process for separately forming contacts to diffusion regions and gate stacks on the semiconductor substrate is used.
摘要翻译：存储锁存器，包括在所述衬底上的栅极绝缘层，穿过所述绝缘层形成的浅沟槽和所述衬底中的沟槽以提供器件绝缘; 以及在浅沟槽之间的衬底中的掺杂区域。掺杂区域定义源和漏极。栅极堆叠形成在与掺杂区域相邻的氧化物区域上。在栅极堆叠之间形成平坦化的绝缘体。在平坦化的绝缘体中提供了开口，用于与掺杂区域和栅极叠层的接触。导电材料填充开口以形成用于掺杂区域和栅极叠层的触点。平坦化绝缘体上的图案化的导电材料层连接用于闩锁的布线部分的所述触点中的所选择的一个。六器件SRAM单元包括形成在衬底中的深隔离沟槽; 第一锁存器，包括在所述沟槽的第一侧上由p型材料形成的两个晶体管; 包括在与沟槽的第一侧相对的沟槽的第二侧上由n型材料形成的两个晶体管的第二锁存器以及用于将第一锁存器的晶体管与第二锁存器的晶体管电交叉布线的连接装置。在形成锁存器时，使用用于单独形成与半导体衬底上的扩散区域和栅极堆叠的接触的自对准工艺。

10. 发明授权

US6143635A Field effect transistors with improved implants and method for making such transistors 失效
标题翻译：具有改进的植入物的场效应晶体管和制造这种晶体管的方法
公开(公告)号：US6143635A
公开(公告)日：2000-11-07
申请号：US374519
申请日：1999-08-16
申请人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
发明人： Diane C. Boyd , Stuart M. Burns , Hussein I. Hanafi , Yuan Taur , William C. Wille
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L29/78 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66583 , H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L29/66537
摘要： Metal oxide semiconductor field effect transistor (MOSFET) including a drain region and a source region adjacent to a channel region. A gate oxide is situated on the channel region and a gate conductor with vertical side walls is placed on the gate oxide. The MOSFET further includes a threshold adjust implant region and/or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor. Such a MOSFET can be made using the following method: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack having the lateral size and shape of a gate hole to be formed; defining the gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; implanting threshold adjust dopants and/or punch through dopants through the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering portions of the semiconductor structure surrounding the gate hole; and removing at least part of the dielectric stack.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）包括漏极区域和与沟道区域相邻的源极区域。栅极氧化物位于沟道区域上，并且具有垂直侧壁的栅极导体被放置在栅极氧化物上。 MOSFET还包括阈值调整注入区域和/或冲孔穿入注入区域，其相对于栅极导体对齐并且限制在栅极导体下方的区域。这样的MOSFET可以使用以下方法制造：在半导体结构上形成介电堆叠; 在所述电介质堆叠上限定具有要形成的栅极孔的横向尺寸和形状的蚀刻窗口; 通过使用反应离子蚀刻（RIE）工艺将蚀刻窗口转移到电介质堆叠中来限定电介质叠层中的栅极孔; 植入阈值调节掺杂剂和/或穿过掺杂剂通过栅极孔; 沉积栅极导体，使其填充栅极孔; 去除覆盖围绕门孔的半导体结构的部分的栅极导体; 以及去除所述电介质叠层的至少一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式