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1. 发明授权

US4985834A System and method employing pipelined parallel circuit architecture for displaying surface structures of the interior region of a solid body 失效
标题翻译：采用流水线并联电路架构的系统和方法，用于显示固体的内部区域的表面结构
公开(公告)号：US4985834A
公开(公告)日：1991-01-15
申请号：US275154
申请日：1988-11-22
申请人： Harvey E. Cline , Richard I. Hartley , Siegwalt Ludke , Sharbel E. Noujaim
发明人： Harvey E. Cline , Richard I. Hartley , Siegwalt Ludke , Sharbel E. Noujaim
IPC分类号： G01N9/24 , G06T1/00 , G06T1/20 , G06T7/60 , G06T11/00 , G06T17/00
CPC分类号： G06T17/00
摘要： Arbitrary interior surfaces of a three-dimensional body are displayed from a regular array of values of at least one physical property in the interior of the body. The physical property measurements may be made with systems such as computerized tomographic x-ray, or magnetic resonance imaging. Highly parallel circuits and a highly parallel architecture permit generation of surface views in real time, i.e., sufficiently fast to support ongoing procedures such as surgical operations. These parallel circuits, realizable on large scale integrated circuit chips, perform surface normal calculations, linear interpolations and signal comparisons in simultaneously operating circuit paths which are asynchronously enabled when input data appear.
摘要翻译：三维身体的任意内表面从身体内部的至少一个物理性质的规则数组中显示出来。物理性质测量可以用诸如计算机断层X射线或磁共振成像的系统进行。高度并行的电路和高度平行的架构允许实时地产生表面视图，即足够快以支持正在进行的程序，例如外科手术。这些并行电路可在大规模集成电路芯片上实现，可在同时工作的电路路径中进行表面正常计算，线性内插和信号比较，并在输入数据出现时异步启用。

2. 发明授权

US4939687A Serial-parallel multipliers using serial as well as parallel addition of partial products 失效
标题翻译：使用串行和并行添加部分产品的串行并行乘法器
公开(公告)号：US4939687A
公开(公告)日：1990-07-03
申请号：US265734
申请日：1988-11-01
申请人： Richard I. Hartley , Sharbel E. Noujaim
发明人： Richard I. Hartley , Sharbel E. Noujaim
IPC分类号： G06F7/52
CPC分类号： G06F7/5275 , G06F2207/3896
摘要： A cell module which is particularly employable in bit-serial silicon compilation methods permits the fabrication and layout of bit-serial multipliers having variable word sizes. In particular, the cell module permits the fabrication of a bit-serial multiplier which is capable of a number of different functions including the production of high-order (major) and low-order (minor) output product bit streams which may be selected from so as to provide output results in a variety of different formats associated with binary fractional multiplication.
摘要翻译：特别可用于比特串行硅编译方法的单元模块允许具有可变字大小的位串行乘法器的制造和布局。特别地，单元模块允许制造能够具有多个不同功能的位串行乘法器，包括产生高阶（主）和低阶（次）输出产品位流，其可以从以便提供与二进制分数乘法相关联的各种不同格式的输出结果。

3. 发明授权

US5034908A Digit-serial transversal filters 失效
标题翻译：数字串行横向滤波器
公开(公告)号：US5034908A
公开(公告)日：1991-07-23
申请号：US504503
申请日：1990-04-02
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00
摘要： One type of transversal filter using digit-serial signals in its operation comprises a to-digit-serial converter for converting a succession of input data words received at its input port each to a respective succession of m-bit-wide digits supplied from its output port in order of progressively greater significance, m being a positive plural integer; a clocked delay line having an input tap connected for responding to the m-bit-wide digits supplied from the output port of the to-digit-serial converter and having at least one further tap for supplying a respective tap signal; and means for performing a weighted summation of the input signal to the clocked delay line and each tap signal from the clocked delay line, to generate a filter response in digit-serial format. Another type of transversal filter, which uses digit-serial signals in its operation, comprises a plurality, p in number, of parallel-to-digit-serial converters, each for generating a respective m-bit-wide digit-serial data stream by converting n-parallel-bit words in an input signal to the digital filter, m being a positive integer and n being the product of m and p; a plurality of tapped delay lines having respective input taps connected from respective ones of said parallel-to-digit-serial converters and each having at least one further tap; means for generating p different phases of filter response in digit-serial form by weighting and summing digital signals taken from respective taps on ones of the p tapped delay lines; and p digit-serial-to-parallel converters for converting, on a cyclic basis, the different phases of filter response to parallel-bit words in an output signal from the digital filter.
摘要翻译：在其操作中使用数字串行信号的一种类型的横向滤波器包括一个数字串行转换器，用于将在其输入端口处接收的一系列输入数据字转换成从其输出端提供的各个相继的m位宽数字端口按顺序逐渐显现，m为正整数; 时钟延迟线具有连接的输入抽头，用于响应从位数字串行转换器的输出端口提供的m位宽数字，并具有用于提供相应抽头信号的至少一个另外的抽头; 以及用于对来自时钟延迟线的时钟延迟线和每个抽头信号执行输入信号的加权求和的装置，以产生数字串行格式的滤波器响应。在其操作中使用数字串行信号的另一种类型的横向滤波器包括多个并行数字串行转换器，每个转换器用于通过以下步骤产生相应的m位宽数字串行数据流：将输入信号中的n个并行位字转换为数字滤波器，m是正整数，n是m和p的乘积; 多个抽头延迟线，其具有从相应的所述并行到数字串行转换器连接的各个输入抽头，并且每个具有至少一个另外的抽头; 用于以数字串行形式产生滤波器响应的p个不同相位的装置，用于通过对从所述p个抽头延迟线中的一个上的各个抽头获得的数字信号进行加权和求和; 和p位串行到并行转换器，用于在来自数字滤波器的输出信号中循环地将滤波器响应的不同相位转换成并行位字。

4. 发明授权

US5164724A Data format converters for use with digit-serial signals 失效
标题翻译：用于数字串行信号的数据格式转换器
公开(公告)号：US5164724A
公开(公告)日：1992-11-17
申请号：US553914
申请日：1990-07-16
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00 , G06F2207/386 , G06F2207/3896
摘要： Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.
摘要翻译：转换装置用于将数字数据字转换为数字串行数据格式，其中数字位宽对于数字数据字的后续处理是最佳的。关于吞吐量效率的优化是与集成电路的吞吐率成比例的集成电路性能的量度，并且与集成电路的面积成反比，其包括处理电路和伴随的转换电路。

5. 发明授权

US4942396A To-digit-serial converters for systems processing data in digit-serial format 失效
标题翻译：用于以数字串行格式处理数据的系统的数位串行转换器
公开(公告)号：US4942396A
公开(公告)日：1990-07-17
申请号：US347860
申请日：1989-05-04
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00 , G06F2207/386 , G06F2207/3896
摘要： Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.
摘要翻译：转换装置用于将数字数据字转换为数字串行数据格式，其中数字位宽对于数字数据字的后续处理是最佳的。关于吞吐量效率的优化是与集成电路的吞吐率成比例的集成电路性能的量度，并且与集成电路的面积成反比，其包括处理电路和伴随的转换电路。

6. 发明授权

US4982353A Subsampling time-domain digital filter using sparsely clocked output latch 失效
标题翻译：使用稀疏时钟输出锁存器的子采样时域数字滤波器
公开(公告)号：US4982353A
公开(公告)日：1991-01-01
申请号：US414869
申请日：1989-09-28
申请人： Philippe L. Jacob , Sharbel E. Noujaim , Glenn A. Forman , John A. Mallick
发明人： Philippe L. Jacob , Sharbel E. Noujaim , Glenn A. Forman , John A. Mallick
IPC分类号： G06F5/06 , G06F7/62
CPC分类号： G06F7/62 , G06F5/06
摘要： The plural-phase clocking signal used in a subsampling time-domain digital filter is partially blanked to generate a sparse clocking signal for a clocked data latch that decimates the output signal from the digital filter, to supply it at a subsampling rate as compared to the sampling rate of input signal to the filter. The blanking signal is generated from a counter that counts occurrences of pulses in the plural-phase clocking signal, which counter comprises a ripple-carry adder and another clocked data latch arranged to accumulate successive unit values. This procedure guarantees correct timing of clocking signal for the output latch vis-a-vis the plural-phase clocking signal used in the preceding time-domain digital filter despite the time taken for carry ripplethrough in the counter adder. Digital hardware is conserved by blanking only one phase of the plural-phase clocking signals.
摘要翻译：在子采样时域数字滤波器中使用的多相时钟信号被部分消隐，以产生用于对来自数字滤波器的输出信号进行抽取的时钟数据锁存器的稀疏时钟信号，以将其与子采样时间信号输入信号到滤波器的采样率。消隐信号由计数器产生，该计数器对多相时钟信号中的脉冲发生进行计数，该计数器包括纹波进位加法器和另一个计时数据锁存器，被布置为累积连续的单位值。尽管在计数器加法器中进行进位纹波的时间，该过程保证输出锁存器对于前一时域数字滤波器中使用的多相时钟信号的时钟信号的正确定时。数字硬件通过仅消除多相时钟信号的一相来节省。

7. 发明授权

US5203335A Phased array ultrasonic beam forming using oversampled A/D converters 失效
标题翻译：使用过采样A / D转换器的相控阵超声波束形成
公开(公告)号：US5203335A
公开(公告)日：1993-04-20
申请号：US844031
申请日：1992-03-02
申请人： Sharbel E. Noujaim , Steven L. Garverick , Matthew O'Donnell
发明人： Sharbel E. Noujaim , Steven L. Garverick , Matthew O'Donnell
IPC分类号： A61B8/14 , G01N29/06 , G01S15/89 , G10K11/34
CPC分类号： G10K11/346 , G01N29/0645 , G01S15/8909 , G01S7/52028
摘要： A beam former in a PASS ultrasonic imaging system includes a set of sigma-delta modulators which operate to separately digitize the received echo signal from each transducer element. The oversampled one-bit digital representations of each echo signal are delayed as required for beam steering and focusing, and are summed together. A decimator filter reduces the sample rate of the digitized receive beam prior to display of the image resulting from the receive beam.

8. 发明授权

US4839652A Method and apparatus for high speed digital phased array coherent imaging system 失效
标题翻译：高速数字相控阵相干成像系统的方法与装置
公开(公告)号：US4839652A
公开(公告)日：1989-06-13
申请号：US56177
申请日：1987-06-01
申请人： Matthew O'Donnell , William E. Engeler , Thomas L. Vogelsong , Steven G. Karr , Sharbel E. Noujaim
发明人： Matthew O'Donnell , William E. Engeler , Thomas L. Vogelsong , Steven G. Karr , Sharbel E. Noujaim
IPC分类号： G06F3/05 , A61B8/00 , G01S7/52 , G01S7/523 , G01S15/89 , G10K11/34 , H03H17/00 , H03H17/06
CPC分类号： H03H17/0664 , G01S15/8918 , G01S7/52034 , G01S7/52046 , G10K11/346 , H03H2218/04
摘要： A method for generating an output stream of digital data words, with each data word representing the amplitude of an analog signal at one of a multiplicity F samples each second and with substantially equally spaced time intervals T therebetween, is obtained from a digital baseband demodulation system used for array beam forming. A data stream, formed of interleaved ADC output digital data words acquired from a set of converters, is at a rate of F total samples/second. Subsequent digital demodulation, filtration, and decimation provides digital output signals which need less delay resolution prior to the formation of coherent sum signals, thereby reducing overall channel memory requirements. The output baseband data stream has enhanced dynamic range, thereby reducing the ADC bit density requirements.

9. 发明授权

US4766416A Circuit for generating the square of a function without multipliers 失效
标题翻译：用于生成没有乘数的函数的平方的电路
公开(公告)号：US4766416A
公开(公告)日：1988-08-23
申请号：US74374
申请日：1987-07-16
申请人： Sharbel E. Noujaim
发明人： Sharbel E. Noujaim
IPC分类号： G06J1/00 , H02H1/00 , H03M1/00
CPC分类号： H02H1/0007 , G06J1/00
摘要： A pair of feedback accumulators are employed in conjunction with an oversampled analog to digital converter to generate the squared binary representation of the analog input signal. Advantage is taken of the particular form of the output waveform from oversampled analog to digital converter circuits to generate not only a standard digital output, but also the squared output after a plurality of bit-time periods L. The circuit avoids the utilization of digital multiplier circuits to perform the squaring function. The circuit is particularly applicable in the construction of electronic circuit breakers which must compute a binary representation of the square of an analog input current level signal, I.sup.2.
摘要翻译：一对反馈累加器与过采样模数转换器结合使用以产生模拟输入信号的平方二进制表示。优点来自过采样模数转换器电路的输出波形的特定形式，不仅产生标准数字输出，而且在多个位时间段L之后产生平方输出。该电路避免了数字乘法器的使用执行平方功能的电路。该电路特别适用于必须计算模拟输入电平电平信号I2的二进制表示的电子断路器的构造。

10. 发明授权

US4630299A Digital circuit for decoding digitized, demodulated FM stereo signals 失效
标题翻译：用于解码数字化，解调FM立体声信号的数字电路
公开(公告)号：US4630299A
公开(公告)日：1986-12-16
申请号：US704123
申请日：1985-02-22
申请人： Kenneth B. Welles, II , Sharbel E. Noujaim , Jerome J. Tiemann
发明人： Kenneth B. Welles, II , Sharbel E. Noujaim , Jerome J. Tiemann
IPC分类号： H03H17/00 , H03H17/02 , H03H17/04 , H04B1/16 , H04H1/00 , H04H20/48 , H04H5/00
CPC分类号： H04H20/48 , H03H17/04 , H04B1/1646
摘要： A simple digital filter having only a single multiplier operates to extract the pilot tone from a demodulated and digitized FM stereo signal. The number of poles in the filter is chosen so that the filter output is also usable to produce a digitized representation of the carrier tone for the left minus right stereo channel. This signal is in turn used to decode the input representation into the desired left and right channel signals. The circuit of the present invention is particularly amenable to fabrication on an integrated circuit chip.
摘要翻译：仅具有单个乘法器的简单数字滤波器用于从解调和数字化的FM立体声信号中提取导频音。选择滤波器中的极数，使得滤波器输出也可用于产生用于左减右立体声道的载波音调的数字化表示。该信号又用于将输入表示解码为期望的左和右声道信号。本发明的电路特别适合在集成电路芯片上制造。

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