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1. 发明公开

CN1197952A 加法电路无效
公开(公告)号：CN1197952A
公开(公告)日：1998-11-04
申请号：CN98105995.3
申请日：1998-04-15
申请人：株式会社鹰山
发明人：寿国梁 , 本桥一则 , 陈颍 , 户松隆 , 周长明 , 陈桀
IPC分类号： G06F7/42 , G06F7/38
CPC分类号： G06F7/49 , G06F2207/386
摘要：多值加法器包括,对多值输入的各位相加的并行加法单元、和将由该位的并行加法单元1－i输出的中间相加和Wi与一个低位数位的进位Ci－1相加的输出加法单元2－i。并行加法单元包括对各位的输入值进行相加的加法单元、将多值输出转换为数字数据的量化单元、将数字数据转换为“中间和”输出和进位输出的逻辑转换单元。上述单元由电压型电路构成。加权加法电路对电容耦合以并联方式连接可变的附加电容负荷,并根据电容耦合的负荷状况控制附加电容负荷。

2. 发明授权

US5241493A Floating point arithmetic unit with size efficient pipelined multiply-add architecture 失效
标题翻译：浮动点算术单元，尺寸有效的管道多用途建筑
公开(公告)号：US5241493A
公开(公告)日：1993-08-31
申请号：US807697
申请日：1991-12-16
申请人： Tan V. Chu , Faraydon O. Karim , Christopher H. Olson
发明人： Tan V. Chu , Faraydon O. Karim , Christopher H. Olson
IPC分类号： G06F7/487 , G06F7/527 , G06F7/533 , G06F7/544
CPC分类号： G06F7/5443 , G06F2207/386 , G06F2207/3884 , G06F7/483
摘要： An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.

3. 发明公开

EP0602888A1 Performing arithmetic operations on data 失效
标题翻译： Durchführungaritmetische Operationen auf Daten。
公开(公告)号：EP0602888A1
公开(公告)日：1994-06-22
申请号：EP93309863.4
申请日：1993-12-08
申请人： XEROX CORPORATION
发明人： Davies, Daniel
IPC分类号： G06F7/48 , G06F7/50
CPC分类号： G06F7/505 , G06F7/48 , G06F9/30036 , G06F2207/3828 , G06F2207/386
摘要： Arithmetic operations are performed on composite operands that include plural component data items. The operations obtain valid results even though the operations would ordinarily produce inter-component signals, such as carry or borrow signals or a shifted bit, causing invalid results. For example, the component data items can be pixel values or other data relating to pixels in an image. Instructions on a storage medium (62) can be accessed and executed by a processor (66) to obtain valid results despite inter-component signals. Or special circuitry, such as gating circuitry or a mask register, can be used to prevent inter-component signals. Components in composite operands can be separated by buffer bits that are cleared or set to ensure valid results. Values of components can be biased before an operation to obtain valid results.
摘要翻译：对包含多个组件数据项的复合操作数执行算术运算。即使操作通常产生分量间信号，例如进位或借位信号或偏移位，导致无效结果，操作获得有效结果。例如，分量数据项可以是与图像中的像素相关的像素值或其他数据。存储介质（62）上的指令可由处理器（66）访问和执行，以获得尽管分量间信号的有效结果。或者可以使用诸如门控电路或屏蔽寄存器的特殊电路来防止分量间信号。复合操作数中的组件可以被清除或设置为保证有效结果的缓冲区分隔开。组件的值可以在操作之前被偏置以获得有效的结果。

4. 发明公开

EP0547835A2 An electronic circuit for performing floating point arithmetic functions 失效
标题翻译： Elektronische Schaltung zumAusführenvon arithmetischen Funktionen mit Gleitkommazahlen。
公开(公告)号：EP0547835A2
公开(公告)日：1993-06-23
申请号：EP92311237.9
申请日：1992-12-09
申请人： International Business Machines Corporation
发明人： Chu, Tan V. , Karim, Faraydon Osmond , Olson, Christopher Hans
IPC分类号： G06F7/544
CPC分类号： G06F7/5443 , G06F7/483 , G06F2207/386 , G06F2207/3884
摘要： An electronic circuit is disclosed for performing the floating point arithmetic operation A * B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A * B+C while using a full adder of three-quarters normal size.
摘要翻译：公开了一种用于执行浮点算术运算A * B + C的电子电路。乘法在两个或更多个阶段完成，每个阶段涉及相应的部分产品集合并且同时完成增量求和。流水线架构在进入全加器之前的阶段提供了中间产品的最低有效位与操作数C的相加。因此，全加器的重要部分可以被更简单和更小的加法器电路代替。将乘法运算分为两个或多个部分乘积运算，按比例缩小所需乘法器的大小。乘法和并行执行乘法和加法运算在乘法器中提供了数学运算A * B + C的结果，同时使用正常大小为四分之三的全加法器。

5. 发明授权

US06295597B1 Apparatus and method for improved vector processing to support extended-length integer arithmetic 有权
标题翻译：用于改进矢量处理以支持扩展长整数运算的装置和方法
公开(公告)号：US06295597B1
公开(公告)日：2001-09-25
申请号：US09132205
申请日：1998-08-11
申请人： David Resnick , William T. Moore
发明人： David Resnick , William T. Moore
IPC分类号： G06F1500
CPC分类号： G06F7/505 , G06F7/50 , G06F15/8076 , G06F2207/386
摘要： An apparatus and a method for extended-precision vector arithmetic capable of extremely long precision (i.e., precision to as many bits as a user desires or is limited to due to memory, disk-storage, or other resource constraints). Vector carry-out bits can be used as vector carry-in bits for successive operations. In performing add or subtract operations on integers that are longer than the word size of the computer, the operands a broken into word-sized parts which are used as operands. A vector of long-integer numbers is thus broken into a series of sub-vectors, each having word-sized elements. Vector add or subtract operations are performed successively on the sub-vectors, starting with the lowest-order sub-vectors. Carry-out (or borrow-out) bits from a first vector operation are used as carry-in (or borrow-in) bits for a successive vector operation. In one embodiment, instructions are added to the instruction set of a vector processor to assist in propagating carry (or borrow) bits between components of long operands, and to assist users in accessing and controlling the carry (or borrow) bits.
摘要翻译：一种用于扩展精度矢量运算的装置和方法，其能够非常长的精度（即，精度达到用户期望的位数或由于存储器，磁盘存储或其他资源约束而被限制）。向量进位位可用作连续操作的向量进位位。在对长于计算机的字大小的整数执行加法或减法操作时，操作数被分解成用作操作数的字大小的部分。因此，长整数的向量被分解成一系列子向量，每个子向量具有字大小的元素。在子向量上连续执行矢量加减运算，从最低阶子向量开始。从第一个矢量运算的进位（或借出）位用作连续矢量运算的进位（或借位）位。在一个实施例中，将指令添加到向量处理器的指令集中以辅助在长操作数的组件之间传播进位（或借位）位，并且帮助用户访问和控制进位（或借位）位。

6. 发明授权

US5408670A Performing arithmetic in parallel on composite operands with packed multi-bit components 失效
标题翻译：在具有打包的多位组件的复合操作数上并行执行算术
公开(公告)号：US5408670A
公开(公告)日：1995-04-18
申请号：US993925
申请日：1992-12-18
申请人： Daniel Davies
发明人： Daniel Davies
IPC分类号： G06F7/48 , G06F7/50 , G06F7/505 , G06F7/506 , G06F15/80
CPC分类号： G06F7/505 , G06F7/48 , G06F9/30036 , G06F2207/3828 , G06F2207/386
摘要： Arithmetic operations are performed on composite operands that include plural component data items. The operations obtain valid results even though the operations would ordinarily produce inter-component signals, such as carry or borrow signals or a shifted bit, causing invalid results. For example, the component data items can be pixel values or other data relating to pixels in an image. Instructions on a storage medium can be accessed and executed by a processor to obtain valid results despite intercomponent signals. Or special circuitry, such as gating circuitry or a mask register, can be used to prevent inter-component signals. Components in composite operands can be separated by buffer bits that are cleared or set to ensure valid results. Values of components can be biased before an operation to obtain valid results.
摘要翻译：对包含多个组件数据项的复合操作数执行算术运算。即使操作通常产生分量间信号，例如进位或借位信号或偏移位，导致无效结果，操作获得有效结果。例如，分量数据项可以是与图像中的像素相关的像素值或其他数据。处理器可以访问和执行存储介质上的指令，以获得尽管组件间信号的有效结果。或者可以使用特殊电路，例如门控电路或屏蔽寄存器来防止分量间信号。复合操作数中的组件可以被清除或设置为保证有效结果的缓冲区分隔开。组件的值可以在操作之前被偏置以获得有效的结果。

7. 发明授权

US5128892A Parallel adder 失效
标题翻译：并行添加
公开(公告)号：US5128892A
公开(公告)日：1992-07-07
申请号：US688187
申请日：1991-04-19
申请人： Manfred Ullrich
发明人： Manfred Ullrich
IPC分类号： G06F7/505 , G06F7/50 , G06F7/506
CPC分类号： G06F7/505 , G06F7/501 , G06F2207/386 , G06F2207/3872
摘要： A parallel adder has a carry between adjacent adding stages. Each of the adding stages includes a carry-generating circuit which generates a carry output signal from carry input signals to be added by the adding stage and a carry input signal applied to it. The carry-generating circuit includes a complementary stage which is built with complementary transistors connected between the two terminals of a supply-voltage source. The carry-generating circuit has a center node which is connected to the carry output terminal and which, if the data input signals applied to the adding stage have the same binary state value, is at a potential corresponding to the binary state value. The carry-generating cricuit further includes a coupling circuit. One end of the coupling circuit is connected to one terminal of the supply-voltage source, and the other end of the coupling circuit is at the potential of the one terminal if the data input signals have unequal binary state values. The carry-generating circuit further includes a switching transistor whose main path is connected between the center node and the other end of the coupling circuit. The control electrode of the switching transistor is supplied with the carry input signal. Each adding stage further includes a presetting device whereby the adding stage, prior to its respective computing cycle, is placed in a preset state representing no carry output.
摘要翻译：并行加法器在相邻的加法阶段之间具有进位。每个添加级包括进位产生电路，其产生来自加法级相加的进位输入信号的进位输出信号和施加到其的进位输入信号。进位产生电路包括互补级，其互补的晶体管被连接在电源电压源的两个端子之间。进位产生电路具有连接到进位输出端的中心节点，如果施加到加法阶段的数据输入信号具有相同的二进制状态值，则其处于与二进制状态值相对应的电位。进位产生乘客还包括耦合电路。耦合电路的一端连接到电源电压源的一个端子，如果数据输入信号具有不相等的二进制状态值，则耦合电路的另一端处于一个端子的电位。进位发生电路还包括开关晶体管，其主路连接在耦合电路的中心节点和另一端之间。开关晶体管的控制电极被提供有进位输入信号。每个添加阶段还包括预设装置，由此在其各自的计算周期之前，添加阶段被置于不表示进位输出的预置状态。

8. 发明申请

WO00052568A1 N BIT BY M BIT MULTIPLICATION OF TWOS COMPLEMENT NUMBERS USING N/2+1 x M/2+1 BIT MULTIPLIERS 审中-公开
标题翻译：使用N / 2 + 1 x M / 2 + 1位多路复用器的双位补码编号的位数N位
公开(公告)号：WO00052568A1
公开(公告)日：2000-09-08
申请号：PCT/EP2000/000740
申请日：2000-01-31
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/525 , G06F2207/386
摘要： The operands of an N x M bit multiplication are partitioned into N/j+1 and M/k+1 bit signed submultiples. The most significant submultiple is assigned the sign of the operand, while each of the less significant submultiples is assigned a positive sign. The product of each submultiple pair is sign extended to the width of the product (N + M), and the accumulation of these sign extended submultiple products provides the product of the original twos complement operands, in twos complement form.
摘要翻译： N×M位乘法的操作数被划分为N / j + 1和M / k + 1位有符号的分数。最重要的分数被分配为操作数的符号，而每个较不重要的乘数被分配一个正号。每个子多对的乘积符号扩展到产品的宽度（N + M），并且这些符号扩展的多项产品的积累提供了二进制补码形式的原始二进制补码操作数的乘积。

9. 发明公开

EP0547835A3 An electronic circuit for performing floating point arithmetic functions 失效
标题翻译：用于执行浮点算术功能的电子电路
公开(公告)号：EP0547835A3
公开(公告)日：1993-08-18
申请号：EP92311237.9
申请日：1992-12-09
申请人： International Business Machines Corporation
发明人： Chu, Tan V. , Karim, Faraydon Osmond , Olson, Christopher Hans
IPC分类号： G06F7/544
CPC分类号： G06F7/5443 , G06F7/483 , G06F2207/386 , G06F2207/3884
摘要： An electronic circuit is disclosed for performing the floating point arithmetic operation A * B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A * B+C while using a full adder of three-quarters normal size.

10. 发明公开

EP0453600A1 Paralleladdierwerk 失效
标题翻译： Paralleladdierwerk。
公开(公告)号：EP0453600A1
公开(公告)日：1991-10-30
申请号：EP90107878.2
申请日：1990-04-25
申请人： Deutsche ITT Industries GmbH
发明人： Ullrich, Manfred, Dipl.-Ing. (FH)
IPC分类号： G06F7/50
CPC分类号： G06F7/505 , G06F7/501 , G06F2207/386 , G06F2207/3872
摘要： Paralleladdierwerk mit Übertrag zwischen benachbarten Addierstufen, wobei jede Addierstufe eine Übertragbildungsschaltung (CT) aufweist, die aus von der Addierstufe zu addierenden Eingangsdatensignalen und einem ihr zugeführten Eingangsübertragsignal ein Ausgangsübertragsignal erzeugt. Dabei weist die Übertragbildungsschaltung (CT) eine mit komplementären Transistoren aufgebaute, zwischen die beiden Pole (+V, -V) einer Spannungsversorgungsquelle geschaltete Komplementärstufe (CS) auf. Diese weist einen mit dem Übertragausgang (CA) verbundenen Mittelknoten (K) auf, der bei gleichem Binärwert der der Addierstufe zugeführten Eingangsdatensignale ein diesem Binärwert entsprechendes Potential aufweist. Die Übertragbildungsschaltung enthält außerdem eine Koppelschaltung (PKS; NKS), die einen Endes mit einem Pol der Spannungsversorgungsquelle verbunden ist und deren anderes Ende (M1; M2) bei ungleichen Binärwerten der Eingangssignaldaten das Potential des einen Pols (+V, -V) aufweist. Die Übertragbildungsschaltung enthält ferner einen Schalttransistor (T5; T6), dessen Hauptstrecke zwischen den Mittelknoten (K) und das andere Ende (M1; M2) der Koppelschaltung (PKS; NKS) geschaltet ist und dessen Steuerelektrode mit dem Eingangsübertragsignal beaufschlagt wird. Außerdem ist eine Voreinstelleinrichtung (VSA, VSB) vorgesehen, welche die Addierstufe vor deren jeweiligem Rechenzyklus in einen keinen Ausgangsübertrag darstellenden Voreinstellzustand bringt.
摘要翻译：具有带有进相邻的添加阶段之间并行加法器，每一个加法器，用于补充的是，从加法器产生的进位产生电路（CT）的输入数据信号和提供给输入进位信号，一个输出进位信号。在这种情况下连接到一个电压供应源的互补阶段，进位产生电路（CT）包括具有互补晶体管内置，在两极（-V + V）（CS）之间。这有一个与连接到中心节点（K）的进位输出（CA），它与加法器，具有该对应电位的二进制值的输入数据信号的相同的二进制值提供。进位产生电路还包括一个耦合电路（PKS; NKS），它是电源电压源的极的一端，并且其另一端（M1; M2）与输入信号的数据的不相等的二进制值有一个极（+ V，-V）的电位。进位产生电路还包括一个开关晶体管（T5; T6）的中心节点（K）和所述另一端之间，其主要路径;耦合电路的（M1 M2）（PKS; NKS）连接，并且其控制电极与所述进位输入信号。此外，提供了一种预设定装置（VSA，VSB），其在表示预设状态的无进位输出其各自的计算周期之前所带来的加法器。

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