专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130303942A1 IMPLANTABLE PRESSURE SENSOR 审中-公开
标题翻译：可植入压力传感器
公开(公告)号：US20130303942A1
公开(公告)日：2013-11-14
申请号：US13889852
申请日：2013-05-08
申请人： Margot S. Damaser , Steven Majerus , Paul C. Fletter , Steven L. Garverick , Ko Wen , Paul Zaszczurynski
发明人： Margot S. Damaser , Steven Majerus , Paul C. Fletter , Steven L. Garverick , Ko Wen , Paul Zaszczurynski
IPC分类号： A61B5/03 , A61B5/00
CPC分类号： A61B5/03 , A61B5/205 , A61B5/6874 , A61B5/6882 , A61B5/726 , A61B2560/0219
摘要： Systems and methods are provided for in vivo measurement of pressure. An implantable sensor assembly includes a pressure sensor configured to provide an analog signal representing pressure and a signal conditioning component configured to convert the pressure sensor output into a digital signal. A transmitter is configured to transmit the digital signal to an external base unit. A power control unit is configured to dynamically allocate power throughout the implantable sensor assembly, such that during an active measurement interval of the implantable sensor assembly, each of the pressure sensor, the signal conditioning component, and the transmitter are powered only for a portion of the active measurement interval necessary to perform a related function.
摘要翻译：提供了用于体内测量压力的系统和方法。可植入传感器组件包括被配置为提供表示压力的模拟信号的压力传感器和被配置为将压力传感器输出转换成数字信号的信号调节部件。发送器被配置为将数字信号发送到外部基本单元。功率控制单元被配置为在整个可植入传感器组件中动态地分配功率，使得在可植入传感器组件的有效测量间隔期间，压力传感器，信号调节部件和发射器中的每一个仅为一部分执行相关功能所需的主动测量间隔。

2. 发明授权

US06961257B2 Content addressable control system 失效
标题翻译：内容可寻址控制系统
公开(公告)号：US06961257B2
公开(公告)日：2005-11-01
申请号：US10800231
申请日：2004-03-12
申请人： Steven L. Garverick , Michael L. Nagy
发明人： Steven L. Garverick , Michael L. Nagy
IPC分类号： B81B3/00 , G02B6/12 , G02B6/26 , G02B6/34 , G02B6/35 , G02B26/08 , H04Q11/00 , G11C15/00 , G11C8/00
CPC分类号： G02B6/357 , G02B6/266 , G02B6/3512 , G02B6/3518 , G02B6/3556 , G02B6/356 , G02B26/0841 , G02B2006/12104 , H04Q11/0005 , H04Q2011/0022 , H04Q2011/0024 , H04Q2011/003 , H04Q2011/0039 , H04Q2011/0049
摘要： Pulse-width modulation (PWM) control and drive circuitry particularly applicable to an array of electrostatic actuators formed in a micro electromechanical system (MEMS), such as used for optical switching. The high-voltage portion may be incorporated in an integrated circuit having drive cells vertically aligned with the MEMS elements. A control cell associated with each actuator includes a register selectively stored with a desired pulse width. A clocked counter distributes its outputs to all control cells. When the counter matches the register, a polarity signal corresponding to a drive clock is latched and controls the voltage applied to the electrostatic cell. The MEMS element may be a tiltable plate supported in its middle by a torsion beam. Complementary binary signals may drive two capacitors formed across the axis of the beam. The register and comparison logic for each cell may be formed by a content addressable memory.
摘要翻译：脉冲宽度调制（PWM）控制和驱动电路特别适用于微机电系统（MEMS）中形成的静电致动器阵列，例如用于光开关。高压部分可以结合在具有与MEMS元件垂直对准的驱动单元的集成电路中。与每个致动器相关联的控制单元包括选择性地以期望的脉冲宽度存储的寄存器。时钟计数器将其输出分配给所有控制单元。当计数器与寄存器匹配时，锁存与驱动时钟对应的极性信号，并控制施加到静电电池的电压。 MEMS元件可以是通过扭转梁在其中间支撑的可倾斜板。互补的二进制信号可以驱动跨过光束的轴形成的两个电容器。每个单元的寄存器和比较逻辑可以由内容可寻址存储器形成。

3. 发明授权

US06543286B2 High frequency pulse width modulation driver, particularly useful for electrostatically actuated MEMS array 有权
公开(公告)号：US06543286B2
公开(公告)日：2003-04-08
申请号：US09884676
申请日：2001-06-19
申请人： Steven L. Garverick , Michael L. Nagy
发明人： Steven L. Garverick , Michael L. Nagy
IPC分类号： G01P1500
CPC分类号： G02B6/357 , G02B6/266 , G02B6/3512 , G02B6/3518 , G02B6/3556 , G02B6/356 , G02B26/0841 , G02B2006/12104 , H04Q11/0005 , H04Q2011/0022 , H04Q2011/0024 , H04Q2011/003 , H04Q2011/0039 , H04Q2011/0049
摘要： Pulse-width modulation (PWM) drive circuitry particularly applicable to an array of electrostatic actuators formed in a micro electromechanical system (MEMS), such as used for optical switching. A control cell associated with each actuator includes a register selectively stored with a desired pulse width. A clocked counter distributes its outputs to all control cells. When the counter matches the register, a polarity signal corresponding to a drive clock is latched and controls the voltage applied to the electrostatic cell. In a bipolar drive, one actuator electrode is driven by a drive clock; the other, by the latch. The MEMS element may be a tiltable plate supported in its middle by a torsion beam. Complementary binary signals may drive two capacitors formed across the axis of the beam. The register and comparison logic for each cell may be formed by a content addressable memory.

4. 发明授权

US5448747A Analog voltage metering system with programmable bit-serial digital signal processors 失效
标题翻译：具有可编程位串行数字信号处理器的模拟电压计量系统
公开(公告)号：US5448747A
公开(公告)日：1995-09-05
申请号：US250122
申请日：1994-05-27
申请人： Steven L. Garverick , Kenji Fujino
发明人： Steven L. Garverick , Kenji Fujino
IPC分类号： G01R19/00 , G01R21/00 , G01R21/133 , G05B19/042 , G06F7/544 , G06F15/78 , G06F17/10 , G06F7/38
CPC分类号： G06F15/7842 , G05B19/0423 , G06F7/5443 , G06F7/5446 , G01R21/006 , G05B2219/25254
摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.
摘要翻译：可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路，该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，包括一位 - 系列乘法加法处理器。该处理器包括位串行数字乘法器，用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器，用于将第三数字处理器输入信号加到数字产生信号以产生数字和信号，以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器，进入内存系统。可以从传感器输出信号中选择第一个数字处理器输入信号，转换为位串行数字格式。应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间，以及施加到位串行乘法加法处理器的第三数字处理器输入信号。控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令，并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。

5. 发明授权

US08299844B2 System and circuitry to provide stable transconductance for biasing 有权
标题翻译：系统和电路为偏置提供稳定的跨导
公开(公告)号：US08299844B2
公开(公告)日：2012-10-30
申请号：US12407348
申请日：2009-03-19
申请人： Steven L. Garverick , Xinyu Yu
发明人： Steven L. Garverick , Xinyu Yu
IPC分类号： H01L35/00 , G05F1/625 , G05F3/26
CPC分类号： G01L19/086 , G01L1/2256
摘要： An amplifier system can include an input amplifier configured to receive an analog input signal and provide an amplified signal corresponding to the analog input signal. A tracking loop is configured to employ delta modulation for tracking the amplified signal, the tracking loop providing a corresponding output signal. A biasing circuit is configured to adjust a bias current to maintain stable transconductance over temperature variations, the biasing circuit providing at least one bias signal for biasing at least one of the input amplifier and the tracking loop, whereby the circuitry receiving the at least one bias signal exhibits stable performance over the temperature variations. In another embodiment the biasing circuit can be utilized in other applications.
摘要翻译：放大器系统可以包括输入放大器，其被配置为接收模拟输入信号并提供对应于模拟输入信号的放大信号。跟踪环路被配置为采用增量调制来跟踪放大的信号，跟踪环路提供相应的输出信号。偏置电路被配置为调整偏置电流以保持跨越温度变化的稳定跨导，偏置电路提供至少一个偏置信号以偏置输入放大器和跟踪环路中的至少一个，由此接收至少一个偏置的电路信号在温度变化方面表现出稳定的性能。在另一实施例中，偏置电路可用于其它应用。

6. 发明授权

US07852331B2 High-voltage ternary driver using dynamic ground 有权
标题翻译：高压三元驱动器采用动态接地
公开(公告)号：US07852331B2
公开(公告)日：2010-12-14
申请号：US11559500
申请日：2006-11-14
申请人： Steven L. Garverick , Ruchi Kothari
发明人： Steven L. Garverick , Ruchi Kothari
IPC分类号： G09G5/00
CPC分类号： G09G3/34 , G09G3/3622 , G09G2310/0289 , G09G2330/02 , G09G2330/021 , G09G2330/028
摘要： Systems and methods for implementing a ternary driver that provides three voltage levels: a high positive voltage, a high negative voltage and a zero voltage. The ternary driver utilizes a dynamic ground to maintain the mid-level zero voltage level at approximately zero volts allowing for voltage regulation during high voltage scenarios. The dynamic ground can be activated when the measured voltage is outside user defined reference voltage levels.
摘要翻译：用于实现提供三个电压电平的三元驱动器的系统和方法：高正电压，高负电压和零电压。三进制驱动器利用动态接地将中间零电压电平维持在大约零伏，允许在高电压情况下的电压调节。当测量的电压超出用户定义的参考电压电平时，可以激活动态接地。

7. 发明授权

US07562581B2 Wireless sensor platform for harsh environments 失效
标题翻译：用于恶劣环境的无线传感器平台
公开(公告)号：US07562581B2
公开(公告)日：2009-07-21
申请号：US11537488
申请日：2006-09-29
申请人： Steven L. Garverick , Xinyu Yu , Lemi Toygur , Yunli He
发明人： Steven L. Garverick , Xinyu Yu , Lemi Toygur , Yunli He
IPC分类号： H03F3/04 , G01B7/00
CPC分类号： G01L19/086 , G01D3/036
摘要： Reliable and efficient sensing becomes increasingly difficult in harsher environments. A sensing module for high-temperature conditions utilizes a digital, rather than analog, implementation on a wireless platform to achieve good quality data transmission. The module comprises a sensor, integrated circuit, and antenna. The integrated circuit includes an amplifier, A/D converter, decimation filter, and digital transmitter. To operate, an analog signal is received by the sensor, amplified by the amplifier, converted into a digital signal by the A/D converter, filtered by the decimation filter to address the quantization error, and output in digital format by the digital transmitter and antenna.
摘要翻译：更恶劣的环境中，可靠和高效的传感变得越来越困难。用于高温条件的感测模块在无线平台上实现数字而不是模拟实现，以实现高质量的数据传输。该模块包括传感器，集成电路和天线。集成电路包括放大器，A / D转换器，抽取滤波器和数字发射器。为了操作，传感器接收模拟信号，由放大器放大，由A / D转换器转换为数字信号，由抽取滤波器滤波以解决量化误差，并由数字发射机以数字格式输出，天线。

8. 发明授权

US5349676A Data acquisition systems with programmable bit-serial digital signal processors 失效
标题翻译：具有可编程位串行数字信号处理器的数据采集系统
公开(公告)号：US5349676A
公开(公告)日：1994-09-20
申请号：US653935
申请日：1991-02-11
申请人： Steven L. Garverick , Kenji Fujino
发明人： Steven L. Garverick , Kenji Fujino
IPC分类号： G01R19/00 , G01R21/00 , G01R21/133 , G05B19/042 , G06F7/544 , G06F15/78 , G06F17/10 , G06F7/68 , G06F7/70 , G06F9/302
CPC分类号： G06F15/7842 , G05B19/0423 , G06F7/5443 , G06F7/5446 , G01R21/006 , G05B2219/25254
摘要： A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.
摘要翻译：可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路，该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置，以及一些初始处理电路，包括一位 - 系列乘法加法处理器。该处理器包括位串行数字乘法器，用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器，用于将第三数字处理器输入信号加到数字产生信号以产生数字和信号，以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。存储器系统提供用于存储程序指令的存储器，用于存储第二数字处理器输入信号的连续值的存储器，用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器，进入内存系统。可以从传感器输出信号中选择第一个数字处理器输入信号，转换为位串行数字格式。应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间，以及施加到位串行乘法加法处理器的第三数字处理器输入信号。控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令，并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。

9. 发明授权

US5226001A Plural-channel decimation filter, as for sigma-delta analog-to-digital converters 失效
标题翻译：多通道抽取滤波器，如Σ-Δ模数转换器
公开(公告)号：US5226001A
公开(公告)日：1993-07-06
申请号：US726443
申请日：1991-07-05
申请人： Steven L. Garverick
发明人： Steven L. Garverick
IPC分类号： H03M3/00 , H03H17/00 , H03H17/02 , H03H17/06
CPC分类号： H03H17/0292 , H03H17/0664
摘要： A decimation filter in which two filtering processes are carried out on a time-division-multiplexed basis using kernels that are sampled-data representations of triangular waves, one of which triangular waves decrements while the other increments, or vice versa. A digital multiplier receives the time-interleaved kernels as a multiplicand and receives as a multiplier a stream of bits supplied at a rate that is one-quarter that of the filter clock pulses. The digital multiplier applies its product output signal to the addend input port of a parallel-bit adder. The sum output port of this adder connects to a cascade connection of first, second, third and fourth clocked latches. The signal from the output port of the fourth clocked latch is supplied to the augend input port of the adder except during the first four clock pulse durations after the kernel values reach maxima. The signal from the output port of the third clocked latch is supplied to the augend input port of the adder during zeroeth and second clock pulse durations after the kernel values reach maxima, and arithmetic zero is supplied to the augend input port of the adder during the first and third clock pulse durations after the kernel values reach maxima. First and second output signals for the decimation filter are extracted from the output ports of the second and fourth clocked latches. This decimation filter can be used on a single-channel or dual-channel basis.
摘要翻译：一种抽取滤波器，其中使用采用三角波的采样数据表示的内核在时分多路复用的基础上执行两个滤波处理，其中三角波在其它增量之间递减，反之亦然。数字乘法器将时间交织的内核接收为被乘数，并且以比特为滤波器时钟脉冲的四分之一的速率提供的比特流作为乘数接收。数字乘法器将其产品输出信号应用于并行位加法器的加数输入端口。该加法器的和输出端口连接到第一，第二，第三和第四时钟锁存器的级联连接。来自第四时钟锁存器的输出端口的信号被提供给加法器的加法器输入端口，除了在内核值达到最大值之后的前四个时钟脉冲持续时间内。在内核值到达最大值之后的第零个和第二个时钟脉冲持续时间内，来自第三时钟锁存器的输出端口的信号被提供给加法器的加法器输入端口，并且在该值期间算术零被提供给加法器的加法器输入端口内核值达到最大值后的第一和第三个时钟脉冲持续时间。从第二和第四时钟锁存器的输出端口提取用于抽取滤波器的第一和第二输出信号。该抽取滤波器可以在单通道或双通道的基础上使用。

10. 发明授权

US5203335A Phased array ultrasonic beam forming using oversampled A/D converters 失效
标题翻译：使用过采样A / D转换器的相控阵超声波束形成
公开(公告)号：US5203335A
公开(公告)日：1993-04-20
申请号：US844031
申请日：1992-03-02
申请人： Sharbel E. Noujaim , Steven L. Garverick , Matthew O'Donnell
发明人： Sharbel E. Noujaim , Steven L. Garverick , Matthew O'Donnell
IPC分类号： A61B8/14 , G01N29/06 , G01S15/89 , G10K11/34
CPC分类号： G10K11/346 , G01N29/0645 , G01S15/8909 , G01S7/52028
摘要： A beam former in a PASS ultrasonic imaging system includes a set of sigma-delta modulators which operate to separately digitize the received echo signal from each transducer element. The oversampled one-bit digital representations of each echo signal are delayed as required for beam steering and focusing, and are summed together. A decimator filter reduces the sample rate of the digitized receive beam prior to display of the image resulting from the receive beam.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式