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1. 发明授权

US06573728B2 Method and circuit for electrical testing of isolation resistance of large capacitance network 有权
公开(公告)号：US06573728B2
公开(公告)日：2003-06-03
申请号：US09942292
申请日：2001-08-29
申请人： Harsaran S. Bhatia , David C. Long , Kathleen M. Wiley
发明人： Harsaran S. Bhatia , David C. Long , Kathleen M. Wiley
IPC分类号： H01H3102
CPC分类号： G01R31/1227 , G01R31/028
摘要： An apparatus (and method) for testing a DC isolation resistance of a large capacitance network experiencing voltage stress, adds capacitance and resistance to a large resistance network under test, such that the direct current (DC) isolation resistance may be determined without distortion from the alternating current (AC) components of the circuit. The capacitance that is added is determined based on the capacitance of the object, the resistance of the object, and the resistance of the testing apparatus. In one embodiment, because the precise capacitance of the network under test may be unknown, the testing apparatus and method may utilize an additional large capacitor designed to obviate small fluctuations in the capacitance of the network.

2. 发明授权

US06916670B2 Electronic package repair process 失效
标题翻译：电子封装修复过程
公开(公告)号：US06916670B2
公开(公告)日：2005-07-12
申请号：US10358431
申请日：2003-02-04
申请人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
发明人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
IPC分类号： H05K3/46 , H01L21/48 , H01L23/12 , H01L23/498 , H05K1/03 , H05K3/00 , H05K3/22 , H01L21/00
CPC分类号： H05K3/225 , H01L21/4846 , H01L23/49811 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/0029 , H05K3/4629 , H05K2203/173 , Y10T29/49124 , Y10T29/49135 , H01L2924/00
摘要： A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.
摘要翻译：一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。有缺陷的网和修复网各自终止在基板的表面通孔处。使用激光器在基板上和基板上形成点火电路。之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

3. 发明授权

US06823585B2 Method of selective plating on a substrate 失效
标题翻译：在基板上选择性镀覆的方法
公开(公告)号：US06823585B2
公开(公告)日：2004-11-30
申请号：US10249305
申请日：2003-03-28
申请人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
发明人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
IPC分类号： H01R4300
CPC分类号： H05K3/242 , H05K1/0306 , H05K3/0035 , H05K3/048 , H05K3/184 , H05K3/225 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49158 , Y10T29/49163 , Y10T29/49165 , Y10T29/49171 , Y10T29/49172 , Y10T29/49721 , Y10T29/49732 , Y10T29/49737 , Y10T29/49746
摘要： A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.
摘要翻译：在基板上形成表面电镀金属化的方法和结构。将两层胶带施加到基材的表面。通过暴露衬底表面的两层带切割第一路径。第一路径在衬底的顶表面上连接至少一个导电通孔。通过暴露第一层胶带的第二层胶带切割第二条路径。第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。去除胶带时，去除牺牲路径。

4. 发明授权

US07294909B2 Electronic package repair process 有权
标题翻译：电子封装修复过程
公开(公告)号：US07294909B2
公开(公告)日：2007-11-13
申请号：US11099161
申请日：2005-04-05
申请人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
发明人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H05K3/225 , H01L21/4846 , H01L23/49811 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/0029 , H05K3/4629 , H05K2203/173 , Y10T29/49124 , Y10T29/49135 , H01L2924/00
摘要： A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.
摘要翻译：一种多层陶瓷修复工艺，提供了一个新的电气修复路径，以连接顶面通孔。修复路径是建立在有缺陷的网和包含在多层陶瓷基板内的冗余修复网之间。有缺陷的网和修复网各自终止在基板的表面通孔处。使用激光器在基板上和基板上形成点火电路。之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

5. 发明授权

US06713686B2 Apparatus and method for repairing electronic packages 失效
标题翻译：用于修理电子封装的装置和方法
公开(公告)号：US06713686B2
公开(公告)日：2004-03-30
申请号：US10053362
申请日：2002-01-18
申请人： Wiren D. Becker , Dinesh Gupta , Sudipta K. Ray , Robert A. Rita , Herbert I. Stoller , Kathleen M. Wiley
发明人： Wiren D. Becker , Dinesh Gupta , Sudipta K. Ray , Robert A. Rita , Herbert I. Stoller , Kathleen M. Wiley
IPC分类号： H01R1204
CPC分类号： H01L23/5382 , H01L2924/0002 , H01L2924/09701 , H05K1/0292 , H05K1/113 , Y10T29/49155 , H01L2924/00
摘要： A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.
摘要翻译：多芯片模块基板，其布置有在模块的芯片位置的修复通道之间延伸的修理通孔和修复线，通过该维修线可以进行修理以克服模块电路中的缺陷，以及用于实现该电路中的缺陷的修复的方法模块。在第一信号通孔，第二信号通孔以及在第一信号通孔和第二信号通孔之间延伸并且用于电连接第一信号通孔的电路线中的任何一个中可能会发生缺陷。识别出故障电路后，电路的信号通孔被隔离。然后，故障电路的第一信号通路经由具有第一信号的芯片位置的修复通孔经由与具有第二信号通路的芯片位置的修复通路连接，并且具有缺陷电路的第二信号通孔电路经由具有第二信号的芯片位置的修复通路经由与经由具有第一信号通孔的芯片位置的修复通路相连接。

6. 发明授权

US06281692B1 Interposer for maintaining temporary contact between a substrate and a test bed 失效
标题翻译：用于保持基板和试验台之间的临时接触的插入件
公开(公告)号：US06281692B1
公开(公告)日：2001-08-28
申请号：US09166468
申请日：1998-10-05
申请人： Paul F. Bodenweber , Ralph R. Comulada , Mukta S. Farooq , Charles J. Hendricks , Philo B. Hodge , Vincent P. Peterson , Terence W. Spoor , Kathleen M. Wiley , Yuet-Ying Yu
发明人： Paul F. Bodenweber , Ralph R. Comulada , Mukta S. Farooq , Charles J. Hendricks , Philo B. Hodge , Vincent P. Peterson , Terence W. Spoor , Kathleen M. Wiley , Yuet-Ying Yu
IPC分类号： G01R3102
CPC分类号： G01R1/07378
摘要： Disclosed is an interposer and test structure for making contact between a substrate and a test bed. One embodiment of the interposer has a floating, rigid conductive element in a nonconductive body which makes temporary contact between the test bed and the substrate. In another embodiment of the invention, the interposer includes two layers of material, in which one layer includes pogo pins for contacting the substrate and the other layer includes pads for contacting the test bed. The pogo pins are on a grid spacing corresponding to that of the substrate input/output pads while the interposer pads are on a grid spacing corresponding to that of the pogo pin contactors of the test bed.
摘要翻译：公开了一种用于在基板和试验台之间进行接触的插入件和测试结构。插入器的一个实施例在非导体中具有浮动的刚性导电元件，其使得测试台与基板之间暂时接触。在本发明的另一个实施例中，插入件包括两层材料，其中一层包括用于接触衬底的弹簧针，另一层包括用于接触测试台的衬垫。弹簧针位于与衬底输入/输出焊盘相对应的栅格间隔上，而插入垫位于对应于测试台的弹簧针接触器的栅格间隔上。

7. 发明授权

US06255827B1 Search routine for 2-point electrical tester 失效
标题翻译： 2点电气测试仪的搜索程序
公开(公告)号：US06255827B1
公开(公告)日：2001-07-03
申请号：US09302944
申请日：1999-04-30
申请人： Mukta S. Farooq , Vincent P. Peterson , Kathleen M. Wiley
发明人： Mukta S. Farooq , Vincent P. Peterson , Kathleen M. Wiley
IPC分类号： H01H3102
CPC分类号： G01R1/06705
摘要： A system for locating electrically conductive contact points on an integrated circuit semiconductor substrate utilizes capacitance and line continuity measurements to control and direct the movement of a two-point probe tester in order to locate and precisely align each test probe with designated contact points. The system is capable of testing for continuity conditions or defects and perform other related electrical measurements.
摘要翻译：用于在集成电路半导体衬底上定位导电接触点的系统利用电容和线路连续性测量来控制和指导两点探针测试仪的移动，以便将每个测试探针与指定的接触点定位和精确对准。该系统能够测试连续性条件或缺陷，并执行其他相关的电气测量。

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