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1. 发明申请

US20050074979A1 Method for forming ferrocapacitors and FeRAM devices 失效
标题翻译：形成铁电体和FeRAM器件的方法
公开(公告)号：US20050074979A1
公开(公告)日：2005-04-07
申请号：US10678758
申请日：2003-10-02
申请人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
发明人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
IPC分类号： H01L21/02 , H01L21/311 , H01L21/8246 , H01L27/115 , H01L21/302 , H01L21/461
CPC分类号： H01L27/11502 , H01L21/31122 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.
摘要翻译：具有垂直结构的铁电体通过在绝缘体上沉积铁电层的工艺形成。在第一蚀刻阶段中，铁电材料被蚀刻以在其中形成开口，从而使绝缘层基本上完好无损。然后，将导电层沉积到形成在铁电层中的开口中，在开口的侧面形成电极。进行进一步蚀刻以在Al 2 O 3层中形成间隙，用于连接到其下方的导电元件。因此，在进行第二蚀刻步骤的时候，已经有电极覆盖在铁电材料的两侧，其间没有绝缘栅栏。

2. 发明授权

US07316980B2 Method for forming ferrocapacitors and FeRAM devices 失效
标题翻译：形成铁电体和FeRAM器件的方法
公开(公告)号：US07316980B2
公开(公告)日：2008-01-08
申请号：US10678758
申请日：2003-10-02
申请人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
发明人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
IPC分类号： H01L21/302
CPC分类号： H01L27/11502 , H01L21/31122 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.
摘要翻译：具有垂直结构的铁电体通过在绝缘体上沉积铁电体层的工艺形成。在第一蚀刻阶段中，铁电材料被蚀刻以在其中形成开口，从而使绝缘层基本上完好无损。然后，将导电层沉积到形成在铁电层中的开口中，在开口的侧面形成电极。执行进一步蚀刻以在Al 2 O 3层中形成间隙，以便连接到其下方的导电元件。因此，在进行第二蚀刻步骤的时候，已经有电极覆盖在铁电材料的两侧，其间没有绝缘栅栏。

3. 发明授权

US07001780B2 Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
标题翻译：通过该方法形成FeRAM电容器和FeRAM电容器的制造方法
公开(公告)号：US07001780B2
公开(公告)日：2006-02-21
申请号：US10635140
申请日：2003-08-06
申请人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
发明人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
IPC分类号： H01L21/00
CPC分类号： H01L28/86 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/90
摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.
摘要翻译：铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的阻挡元件隔开。阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。这意味着在底电极的蚀刻期间不形成Ir栅栏。此外，很少的Ir和/或IrO 2 <2>通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料的风险。

4. 发明申请

US20050070030A1 Device and method for forming a contact to a top electrode in ferroelectric capacitor devices 审中-公开
标题翻译：在铁电电容器件中形成与顶部电极的接触的装置和方法
公开(公告)号：US20050070030A1
公开(公告)日：2005-03-31
申请号：US10672308
申请日：2003-09-26
申请人： Stefan Gernhardt , Haoren Zhuang , Ulrich Egger
发明人： Stefan Gernhardt , Haoren Zhuang , Ulrich Egger
IPC分类号： H01L21/02 , H01L21/00
CPC分类号： H01L28/60
摘要： A device and method for fabricating a device comprises forming a substrate and forming a contact plug through the substrate. A first electrode is formed on the substrate and a dielectric layer is formed on the first electrode. A second electrode is formed on the ferroelectric layer and an interlayer dielectric layer is applied to the second electrode and exposed surfaces of the first electrode and the ferroelectric layer. The interlayer dielectric layer is subjected to a chemical mechanical polishing process to expose a surface of the second electrode and a metal layer is deposited onto the polished interlayer dielectric layer and the exposed surface of the second electrode. The metal layer is then etched to provide an interconnection pattern to the second electrode.
摘要翻译：用于制造器件的器件和方法包括形成衬底并通过衬底形成接触插塞。在基板上形成第一电极，在第一电极上形成电介质层。在铁电体层上形成第二电极，在第二电极和第一电极和铁电层的露出面上施加层间电介质层。对层间介电层进行化学机械抛光工艺以暴露第二电极的表面，并且将金属层沉积到抛光的层间介电层和第二电极的暴露表面上。然后蚀刻金属层以提供到第二电极的互连图案。

5. 发明申请

US20050029563A1 Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
标题翻译：通过该方法形成FeRAM电容器和FeRAM电容器的制造方法
公开(公告)号：US20050029563A1
公开(公告)日：2005-02-10
申请号：US10635140
申请日：2003-08-06
申请人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
发明人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
IPC分类号： H01L21/02 , H01L21/8246 , H01L31/119
CPC分类号： H01L28/86 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/90
摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.
摘要翻译：铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的屏障元件隔开。阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。这意味着在底电极的蚀刻期间不形成Ir栅栏。另外，少量Ir和/或IrO 2通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料。

6. 发明授权

US06946735B2 Side-wall barrier structure and method of fabrication 有权
标题翻译：侧壁屏障结构及其制造方法
公开(公告)号：US06946735B2
公开(公告)日：2005-09-20
申请号：US10307257
申请日：2002-11-29
申请人： Stefan Gernhardt , Jenny Lian , Andreas Hilliger , Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel
发明人： Stefan Gernhardt , Jenny Lian , Andreas Hilliger , Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48
CPC分类号： H01L21/7687 , H01L21/76877 , H01L28/60
摘要： The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.
摘要翻译：本发明包括具有通过CP接触的多硅插头的晶片。多晶硅插头由相对高掺杂的多晶硅层和相对轻掺杂的多晶硅层形成。相对轻掺杂的多晶硅层通过相对重掺杂的多晶硅层延伸超过相对重掺杂的多晶硅层朝向晶片的表面。阻挡层覆盖相对较轻掺杂的多晶硅层的顶壁和侧壁，用于减少多晶硅插头表面的氧化。通过在CP接触中沉积相对重掺杂的多晶硅层来制造晶片，沉积相对轻掺杂的多晶硅层以通过相对重掺杂的多晶硅层，以及沉积阻挡层以覆盖顶部和侧壁相对轻掺杂的多晶硅层，以减少在多晶硅塞的表面处的氧化。

7. 发明授权

US06839220B1 Multi-layer barrier allowing recovery anneal for ferroelectric capacitors 有权
标题翻译：用于铁电电容器的多层屏障允许恢复退火
公开(公告)号：US06839220B1
公开(公告)日：2005-01-04
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

8. 发明申请

US20050013091A1 MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS 有权
标题翻译：多层障碍物允许用于电容电容器的恢复电极
公开(公告)号：US20050013091A1
公开(公告)日：2005-01-20
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

9. 发明授权

US06940111B2 Radiation protection in integrated circuits 失效
标题翻译：集成电路中的辐射防护
公开(公告)号：US06940111B2
公开(公告)日：2005-09-06
申请号：US10065922
申请日：2002-11-29
申请人： Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel , Stefan Gernhardt
发明人： Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel , Stefan Gernhardt
IPC分类号： G06F1/04 , H01L21/02 , H01L23/00 , H01L23/552 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/552 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.
摘要翻译：公开了降低对IC特征的辐射损伤。对辐射敏感的特征的至少一部分被辐射防护层覆盖。辐射防护层在例如IC的处理期间保护特征不被辐射损坏。在一个实施例中，辐射防护层包括贵金属，氧化物，合金或其化合物。

10. 发明授权

US07061035B2 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US07061035B2
公开(公告)日：2006-06-13
申请号：US10677852
申请日：2003-10-01
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬垫层，并且蚀刻用于VO触点的孔，直到蚀刻被衬垫层停止。

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