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1. 发明申请

US20050074979A1 Method for forming ferrocapacitors and FeRAM devices 失效
标题翻译：形成铁电体和FeRAM器件的方法
公开(公告)号：US20050074979A1
公开(公告)日：2005-04-07
申请号：US10678758
申请日：2003-10-02
申请人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
发明人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
IPC分类号： H01L21/02 , H01L21/311 , H01L21/8246 , H01L27/115 , H01L21/302 , H01L21/461
CPC分类号： H01L27/11502 , H01L21/31122 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.
摘要翻译：具有垂直结构的铁电体通过在绝缘体上沉积铁电层的工艺形成。在第一蚀刻阶段中，铁电材料被蚀刻以在其中形成开口，从而使绝缘层基本上完好无损。然后，将导电层沉积到形成在铁电层中的开口中，在开口的侧面形成电极。进行进一步蚀刻以在Al 2 O 3层中形成间隙，用于连接到其下方的导电元件。因此，在进行第二蚀刻步骤的时候，已经有电极覆盖在铁电材料的两侧，其间没有绝缘栅栏。

2. 发明授权

US07001780B2 Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
标题翻译：通过该方法形成FeRAM电容器和FeRAM电容器的制造方法
公开(公告)号：US07001780B2
公开(公告)日：2006-02-21
申请号：US10635140
申请日：2003-08-06
申请人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
发明人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
IPC分类号： H01L21/00
CPC分类号： H01L28/86 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/90
摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.
摘要翻译：铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的阻挡元件隔开。阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。这意味着在底电极的蚀刻期间不形成Ir栅栏。此外，很少的Ir和/或IrO 2 <2>通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料的风险。

3. 发明授权

US07316980B2 Method for forming ferrocapacitors and FeRAM devices 失效
标题翻译：形成铁电体和FeRAM器件的方法
公开(公告)号：US07316980B2
公开(公告)日：2008-01-08
申请号：US10678758
申请日：2003-10-02
申请人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
发明人： Haoren Zhuang , Ulrich Egger , Rainer Bruchhaus , Karl Hornik , Jenny Lian , Stefan Gernhardt
IPC分类号： H01L21/302
CPC分类号： H01L27/11502 , H01L21/31122 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.
摘要翻译：具有垂直结构的铁电体通过在绝缘体上沉积铁电体层的工艺形成。在第一蚀刻阶段中，铁电材料被蚀刻以在其中形成开口，从而使绝缘层基本上完好无损。然后，将导电层沉积到形成在铁电层中的开口中，在开口的侧面形成电极。执行进一步蚀刻以在Al 2 O 3层中形成间隙，以便连接到其下方的导电元件。因此，在进行第二蚀刻步骤的时候，已经有电极覆盖在铁电材料的两侧，其间没有绝缘栅栏。

4. 发明申请

US20050070030A1 Device and method for forming a contact to a top electrode in ferroelectric capacitor devices 审中-公开
标题翻译：在铁电电容器件中形成与顶部电极的接触的装置和方法
公开(公告)号：US20050070030A1
公开(公告)日：2005-03-31
申请号：US10672308
申请日：2003-09-26
申请人： Stefan Gernhardt , Haoren Zhuang , Ulrich Egger
发明人： Stefan Gernhardt , Haoren Zhuang , Ulrich Egger
IPC分类号： H01L21/02 , H01L21/00
CPC分类号： H01L28/60
摘要： A device and method for fabricating a device comprises forming a substrate and forming a contact plug through the substrate. A first electrode is formed on the substrate and a dielectric layer is formed on the first electrode. A second electrode is formed on the ferroelectric layer and an interlayer dielectric layer is applied to the second electrode and exposed surfaces of the first electrode and the ferroelectric layer. The interlayer dielectric layer is subjected to a chemical mechanical polishing process to expose a surface of the second electrode and a metal layer is deposited onto the polished interlayer dielectric layer and the exposed surface of the second electrode. The metal layer is then etched to provide an interconnection pattern to the second electrode.
摘要翻译：用于制造器件的器件和方法包括形成衬底并通过衬底形成接触插塞。在基板上形成第一电极，在第一电极上形成电介质层。在铁电体层上形成第二电极，在第二电极和第一电极和铁电层的露出面上施加层间电介质层。对层间介电层进行化学机械抛光工艺以暴露第二电极的表面，并且将金属层沉积到抛光的层间介电层和第二电极的暴露表面上。然后蚀刻金属层以提供到第二电极的互连图案。

5. 发明申请

US20050029563A1 Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method 失效
标题翻译：通过该方法形成FeRAM电容器和FeRAM电容器的制造方法
公开(公告)号：US20050029563A1
公开(公告)日：2005-02-10
申请号：US10635140
申请日：2003-08-06
申请人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
发明人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Stefan Gernhardt , Hiroyuki Kanaya
IPC分类号： H01L21/02 , H01L21/8246 , H01L31/119
CPC分类号： H01L28/86 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/90
摘要： A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.
摘要翻译：铁电体元件包括底电极，其上形成有铁电体元件，并且在铁电元件上形成顶电极。底部电极通过导电插头连接到器件的下层，并且插头和底部电极被Ir和/或IrO 2的屏障元件隔开。阻挡元件比底部电极元件窄，并且通过单独的蚀刻工艺形成。这意味着在底电极的蚀刻期间不形成Ir栅栏。另外，少量Ir和/或IrO 2通过底部电极扩散到铁电体元件，因此几乎不会损坏铁电体材料。

6. 发明授权

US06785119B2 Ferroelectric capacitor and process for its manufacture 失效
标题翻译：铁电电容器及其制造工艺
公开(公告)号：US06785119B2
公开(公告)日：2004-08-31
申请号：US10307230
申请日：2002-11-29
申请人： Ulrich Egger , Haoren Zhuang , Karl Hornik
发明人： Ulrich Egger , Haoren Zhuang , Karl Hornik
IPC分类号： H01G4228
CPC分类号： H01L28/55 , H01L21/02178 , H01L21/02266 , H01L21/31116 , H01L21/3162
摘要： Forming a capacitor, by (a) forming a matrix of ferroelectric capacitor elements on a substrate, (b) forming a CAP layer over the ferroelectric capacitor elements, and (c) etching the CAP layer to a more uniform thickness. A capacitor that has a substrate layer, a matrix of ferroelectric capacitor elements including a first electrode layer substantially fixed relative to the substrate, a second electrode layer, and a ferroelectric layer sandwiched between the first and second electrode layers is disclosed. The capacitor has a shoulder layer extending from the substrate to the matrix, and a CAP layer etched to have substantially constant thickness covering sides of the matrix extending beyond the substrate.
摘要翻译：通过（a）在基板上形成铁电电容器元件的矩阵，（b）在铁电电容器元件上形成CAP层，形成电容器，（c）将CAP层蚀刻到更均匀的厚度。公开了具有基板层的电容器，包括相对于基板大致固定的第一电极层的铁电电容器元件的矩阵，第二电极层和夹在第一和第二电极层之间的铁电层。电容器具有从基板延伸到基体的肩层，并且CAP层被蚀刻以具有基本上恒定的厚度，覆盖延伸超过基底的基体的侧面。

7. 发明授权

US07045837B2 Hardmask with high selectivity for Ir barriers for ferroelectric capacitor manufacturing 失效
标题翻译：用于铁电电容器制造的Ir屏障的高选择性硬掩模
公开(公告)号：US07045837B2
公开(公告)日：2006-05-16
申请号：US10356314
申请日：2003-01-31
申请人： Ulrich Egger , Haoren Zhuang , Yoshinoru Kumura , Kazuhiro Tomioka , Hiroyuki Kanaya
发明人： Ulrich Egger , Haoren Zhuang , Yoshinoru Kumura , Kazuhiro Tomioka , Hiroyuki Kanaya
IPC分类号： H01L29/76
CPC分类号： H01L28/65 , H01L21/32136 , H01L21/32139 , H01L28/55
摘要： The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.
摘要翻译：本发明通过使用相对于下层阻挡层具有高蚀刻选择性的硬掩模来提供相对不含栅栏的铁电体元件。本发明还包括一种用于抑制附着在铁电体器件的侧壁上的栅栏的方法。此外，与现有技术的装置相比，本发明提供一种具有与下层阻挡层相比较薄的硬掩模的铁电体装置。

8. 发明授权

US07042705B2 Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing 失效
标题翻译：在CW孔反应离子蚀刻处理期间用于减少氧扩散到接触塞的侧壁结构和制造方法
公开(公告)号：US07042705B2
公开(公告)日：2006-05-09
申请号：US10356690
申请日：2003-01-30
申请人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka , Jingyu Lian , Nicolas Nagel , Andreas Hilliger , Gerhard Beitel
发明人： Haoren Zhuang , Ulrich Egger , Kazuhiro Tomioka , Jingyu Lian , Nicolas Nagel , Andreas Hilliger , Gerhard Beitel
IPC分类号： H01G4/10
CPC分类号： H01L28/55 , H01L21/31116 , H01L28/57
摘要： The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.
摘要翻译：本发明提供一种侧壁氧扩散阻挡层和制造侧壁氧扩散阻挡层的方法，该方法在FeRAM器件的铁电电容器的CW孔反应离子蚀刻期间减少氧气扩散到接触塞中。在一个实施例中，侧壁屏障由衬底围栏形成。在另一个实施例中，通过蚀刻回氧屏障来形成侧壁屏障。

9. 发明授权

US07001781B2 Method for producing a ferroelectric capacitor that includes etching with hardmasks 失效
标题翻译：包括用硬掩模蚀刻的铁电电容器的制造方法
公开(公告)号：US07001781B2
公开(公告)日：2006-02-21
申请号：US10672306
申请日：2003-09-26
申请人： Jenny Lian , Ulrich Egger , Haoren Zhuang
发明人： Jenny Lian , Ulrich Egger , Haoren Zhuang
IPC分类号： H01L21/475
CPC分类号： H01L28/60 , H01L21/31122 , H01L21/32136 , H01L21/32139 , H01L27/11502 , H01L27/11507 , H01L28/57 , H01L28/75
摘要： A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.
摘要翻译：一种用于制造器件和器件的方法，例如铁电电容器，具有衬底，通过衬底的接触插塞，衬底上的第一阻挡层，第一阻挡层上的第一电极，第一阻挡层上的电介质层电极和第二电极，包括使用第一硬掩模蚀刻该器件的第二电极和介电层，以使第二电极和电介质层成型。然后去除第一硬掩模，并且将一个或多个封装层施加到第二电极和电介质层。另外的硬掩模应用于一个或多个封装层。然后根据第二硬掩模将第一电极蚀刻到第一阻挡层，然后从一个或多个封装层移除第二硬掩模。

10. 发明申请

US20050045937A1 FENCE-FREE ETCHING OF IRIDIUM BARRIER HAVING A STEEP TAPER ANGLE 失效
标题翻译：具有椎弓根角度的UM。。。。。。。。。。。。。。。。
公开(公告)号：US20050045937A1
公开(公告)日：2005-03-03
申请号：US10654376
申请日：2003-09-03
申请人： Ulrich Egger , Haoren Zhuang , George Stojakovic , Kazuhiro Tomioka
发明人： Ulrich Egger , Haoren Zhuang , George Stojakovic , Kazuhiro Tomioka
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/8246 , H01L21/00 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L28/60 , H01L21/32136 , H01L27/11507 , H01L28/55 , H01L28/75
摘要： An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.
摘要翻译：铱屏障层位于电容器的接触插塞和底部电极之间。进行蚀刻以使用氟基配方对底部电极和阻挡层进行图案化，从而形成紧贴在侧壁上的第一栅栏。接下来，使用基于CO的配方蚀刻剩余的阻挡层。第二个围栏是由第一个围栏固定在结构上。同时，基于CO的配方消除了第一篱笆的大部分，以移除提供给第二篱笆的结构支撑。因此，第二围栏从侧壁脱离，留下侧壁基本上没有附着的栅栏。蚀刻的阻挡层具有侧壁过渡。侧壁在侧壁过渡之上具有相对较低的锥角，并且在侧壁过渡之下具有相对较陡的锥角。

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