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1. 发明授权

US07378700B2 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US07378700B2
公开(公告)日：2008-05-27
申请号：US11373080
申请日：2006-03-09
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬层，并且蚀刻用于V0接触的孔，直到蚀刻被衬垫层停止。

2. 发明申请

US20050082583A1 Self-aligned Vo-contact for cell size reduction 失效
标题翻译：自对准Vo接触，以减小电池尺寸
公开(公告)号：US20050082583A1
公开(公告)日：2005-04-21
申请号：US10677852
申请日：2003-10-01
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L21/02 , H01L21/60 , H01L29/76
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬垫层，并且蚀刻用于VO触点的孔，直到蚀刻被衬垫层停止。

3. 发明申请

US20060151819A1 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US20060151819A1
公开(公告)日：2006-07-13
申请号：US11373080
申请日：2006-03-09
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬层，并且蚀刻用于V0接触的孔，直到蚀刻被衬垫层停止。

4. 发明申请

US20050013091A1 MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS 有权
标题翻译：多层障碍物允许用于电容电容器的恢复电极
公开(公告)号：US20050013091A1
公开(公告)日：2005-01-20
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

5. 发明授权

US07061035B2 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US07061035B2
公开(公告)日：2006-06-13
申请号：US10677852
申请日：2003-10-01
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬垫层，并且蚀刻用于VO触点的孔，直到蚀刻被衬垫层停止。

6. 发明授权

US06839220B1 Multi-layer barrier allowing recovery anneal for ferroelectric capacitors 有权
标题翻译：用于铁电电容器的多层屏障允许恢复退火
公开(公告)号：US06839220B1
公开(公告)日：2005-01-04
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

7. 发明授权

US06946735B2 Side-wall barrier structure and method of fabrication 有权
标题翻译：侧壁屏障结构及其制造方法
公开(公告)号：US06946735B2
公开(公告)日：2005-09-20
申请号：US10307257
申请日：2002-11-29
申请人： Stefan Gernhardt , Jenny Lian , Andreas Hilliger , Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel
发明人： Stefan Gernhardt , Jenny Lian , Andreas Hilliger , Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48
CPC分类号： H01L21/7687 , H01L21/76877 , H01L28/60
摘要： The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.
摘要翻译：本发明包括具有通过CP接触的多硅插头的晶片。多晶硅插头由相对高掺杂的多晶硅层和相对轻掺杂的多晶硅层形成。相对轻掺杂的多晶硅层通过相对重掺杂的多晶硅层延伸超过相对重掺杂的多晶硅层朝向晶片的表面。阻挡层覆盖相对较轻掺杂的多晶硅层的顶壁和侧壁，用于减少多晶硅插头表面的氧化。通过在CP接触中沉积相对重掺杂的多晶硅层来制造晶片，沉积相对轻掺杂的多晶硅层以通过相对重掺杂的多晶硅层，以及沉积阻挡层以覆盖顶部和侧壁相对轻掺杂的多晶硅层，以减少在多晶硅塞的表面处的氧化。

8. 发明授权

US06940111B2 Radiation protection in integrated circuits 失效
标题翻译：集成电路中的辐射防护
公开(公告)号：US06940111B2
公开(公告)日：2005-09-06
申请号：US10065922
申请日：2002-11-29
申请人： Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel , Stefan Gernhardt
发明人： Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel , Stefan Gernhardt
IPC分类号： G06F1/04 , H01L21/02 , H01L23/00 , H01L23/552 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/552 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.
摘要翻译：公开了降低对IC特征的辐射损伤。对辐射敏感的特征的至少一部分被辐射防护层覆盖。辐射防护层在例如IC的处理期间保护特征不被辐射损坏。在一个实施例中，辐射防护层包括贵金属，氧化物，合金或其化合物。

9. 发明授权

US06815234B2 Reducing stress in integrated circuits 失效
标题翻译：降低集成电路中的应力
公开(公告)号：US06815234B2
公开(公告)日：2004-11-09
申请号：US10248253
申请日：2002-12-31
申请人： Uwe Wellhausen , Stefan Gernhardt , Rainer Bruchhaus , Andreás Hilliger , Jing Yu Lian , Nicolas Nagel
发明人： Uwe Wellhausen , Stefan Gernhardt , Rainer Bruchhaus , Andreás Hilliger , Jing Yu Lian , Nicolas Nagel
IPC分类号： H01L2166
CPC分类号： H01L27/11502 , H01L23/562 , H01L27/11507 , H01L27/1159 , H01L29/7842 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor chip in which stress on the effective stress on the substrate is reduced in order to reduce bowing. To reduce the effective stress, a stress compensation layer is provided on the backside of the chip. The stress compensating layer produces a stress opposite of that produced by the IC. Thus the overall or effective stress on the substrate is reduced.
摘要翻译：为了减少弯曲，半导体芯片对基板上的有效应力的应力减小。为了降低有效应力，在芯片的背面设置应力补偿层。应力补偿层产生与IC产生的应力相反的应力。因此，降低了基板上的整体或有效应力。

10. 发明授权

US06800890B1 Memory architecture with series grouped by cells 失效
标题翻译：存储器体系结构，按单元格分组
公开(公告)号：US06800890B1
公开(公告)日：2004-10-05
申请号：US10248234
申请日：2002-12-30
申请人： Joerg Wohlfahrt , Rainer Bruchhaus , Andreas Hilliger
发明人： Joerg Wohlfahrt , Rainer Bruchhaus , Andreas Hilliger
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/10817 , H01L27/10852 , H01L27/11507
摘要： An IC with a memory array having a series architecture is disclosed. A memory cell of a series group comprises a transistor coupled to a capacitor in parallel. The capacitor includes first and second subcapacitors, one stacked one on top of the other. Providing a capacitor with two or more subcapacitors in a stack advantageously increases the capacitance of a capacitor without increasing surface area.
摘要翻译：公开了具有串联结构的存储器阵列的IC。串联组的存储单元包括并联耦合到电容器的晶体管。电容器包括第一和第二副电容器，一个堆叠在另一个之上。在堆叠中提供具有两个或更多个子电容器的电容器有利地增加电容器的电容而不增加表面积。

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