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1. 发明专利

DE2653833A1 未知
公开(公告)号：DE2653833A1
公开(公告)日：1977-06-08
申请号：DE2653833
申请日：1976-11-26
申请人： HITACHI LTD
发明人： YOSHIMURA MASAYOSHI , OTSUKI KEIZO , SHOJI SENJI , YAMADA TOMIO , SHIMIZU ICHIO , ARAI YUJI
IPC分类号： H01L23/28 , H01L23/495 , H01L23/36
摘要： PURPOSE:To reduce the height of radiation fin, by adjusting the location of the radiation fin, so that one end of the fin laps over the fin adapter plate and the rest of the fin laps over the resin body, and by connecting one end of the fin to the adapter plate.

2. 发明专利

AU6852498A Portable communication equipment 未知
公开(公告)号：AU6852498A
公开(公告)日：1999-11-08
申请号：AU6852498
申请日：1998-04-16
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： HIRASHIMA TOSHINORI , ENDO TSUNEO , MORIKAWA MASATOSHI , HIBINO MITSUAKI , YAMADA TOMIO , KIKUCHI SAKAE , MORIYAMA SHINJI
IPC分类号： H01L23/367 , H04B1/036 , H05K1/02 , H05K1/03 , H05K3/40 , H05K3/46 , H01L25/00 , H01L23/12 , H01L23/36 , H04B1/04
摘要： Portable communication equipment provided with an antenna and a power amplifier circuit module for amplifying high-frequency signals emitted from the antenna, wherein the power amplifier circuit module is provided with a wiring board (1) and a semiconductor element (CHT) (2) which is mounted on the wiring board (1) and electrically and mechanically connected to the board (1) through a plurality of bump electrodes (3), characterized in that the substrate (1) has conductors (4 and 5) which are electrically and mechanically connected to part of the bump electrodes (3) and work as heat dissipating paths. The portable communication equipment is further characterized in that the wiring board (1) is constituted in a multilayered wiring board composed of multiple wiring layers and the conductors (4 and 5) used as the above heat dissipating paths are formed through each wiring layer of the multilayered wiring board, thereby further reducing the size of the power amplifier circuit module and, accordingly, the portable communication equipment.

3. 发明专利

JP2002141454A POWER MOSFET 审中-公开
公开(公告)号：JP2002141454A
公开(公告)日：2002-05-17
申请号：JP2001252530
申请日：2001-08-23
申请人： HITACHI LTD
发明人： YAMADA TOMIO , MURAKAMI HAJIME
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/48 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a MOSFET by suppressing an external resistance part and a thermal resistance. SOLUTION: An electrode pad 21 for a drain of a pellet 10 in which a MOSFET circuit is formed is connected to a header 41 by a high melting point solder. An electrode pad 19 for a gate and an electrode pad 30 for a source of the pellet 10 are respectively connected to inner leads 36 and 37 by connectors 25 and 26 made of low melting point solder bumps. A plurality of branches are provided at the lead 37 for the source, and connected to the pad 20 for the source by a plurality of connectors 26 formed at the branches. The source electrode is connected to the inner leads by a plurality of bump connectors and hence the source electrode of a large current is reduced, and hence its external resistance part can be effectively suppressed. Since a thermal stress can be absorbed by the branches of the inner leads for the source, the connectors made of the plurality of the bumps arranged at the branches can be suitably formed at the source electrode.

4. 发明专利

JP2000228466A SEMICONDUCTOR DEVICE, ITS MANUFACTURE, AND ELECTRONIC DEVICE 失效
公开(公告)号：JP2000228466A
公开(公告)日：2000-08-15
申请号：JP2950899
申请日：1999-02-08
申请人： HITACHI LTD
发明人： NIITSU TOSHIJI , IIZUKA MAMORU , ENDO TSUNEO , YAMADA TOMIO
IPC分类号： H01L23/29
摘要： PROBLEM TO BE SOLVED: To mount a semiconductor device having a high heat value by fitting a metal plate where front and back surfaces for forming the circuit element of a semiconductor chip are bonded and fixed by solder with a high melt point to a wiring board where multilayer circuit interconnection is formed on a resin substrate, and by sealing an electrical connection part with resin. SOLUTION: A heat sink 6 is buried to a wiring board where circuit wiring 2 is formed on a resin substrate 1. On the upper surface of the heat sink 6, the circuit element formation surface (front surface) and opposite surface (back surface) of a semiconductor chip 3 are bonded and fixed by solder 4 with a high melt point for mounting. An electrode pad being formed on the circuit element formation surface of the semiconductor chip 3 is electrically connected to the circuit wiring 2 on the wiring board by a metal wire 5. The semiconductor chip 3, the metal wire 5, the wiring 2 on the wiring board, and each electrical connection part are sealed by a resin sealing body (resin) 7. Then, an insulating layer 8 is provided onto the surface (back surface) where the circuit wiring 2 is not provided onto the resin substrate 1, and the back surface of the heat sink (heat spreader) 6.

5. 发明专利

JPH09331015A SEMICONDUCTOR PACKAGE AND ITS MANUFACTURE 失效
公开(公告)号：JPH09331015A
公开(公告)日：1997-12-22
申请号：JP14888196
申请日：1996-06-11
申请人： HITACHI LTD
发明人： ITO KAZUTOSHI , OHASHI TAKEYA , YAMADA TOMIO
IPC分类号： H01L23/50
摘要： PROBLEM TO BE SOLVED: To suppress the generation of a bridging between pins when a solder plating operation is conducted by a method in which a copper-plated film is formed on the surface of the copper alloy of a substrate only on the outer lead part of a lead frame, and the copper-plated film is coated by a solder-plated film. SOLUTION: A copper-plated film 2 is formed on a Cu-Ni-Si copper alloy outer lead part 6, and a solder-plated film 3 is formed thereon. A semiconductor element 7 is soldered on the semiconductor element mounted part 4 of a lead frame 1 using solder 8, partial Ag-plating 11 is provided on the electrode on a semiconductor element and an inner lead part 5, between the electrode of the semiconductor and the inner lead part 5 is bonded by an Au-wire 9 and sealed by epoxy resin 10. By providing solder plating on the outer lead part 6 through the copper-plated film 2 as above-mentioned, the growth of solder is suppressed. Consequently, as the outer lead part 6 is covered by the solder- plated film 3, the reliability of the semiconductor can be improved by the oxidation preventing effect of the copper alloy lead part.

6. 发明专利

JPH09307103A COMPOSITE TYPE SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH09307103A
公开(公告)日：1997-11-28
申请号：JP12021196
申请日：1996-05-15
申请人： HITACHI LTD
发明人： SAKAMOTO MITSUZO , YAMADA TOMIO
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/04 , H01L27/088
摘要： PROBLEM TO BE SOLVED: To realize low ON-resistance and maintain pin compatibility with an element power MOSFET, in a composite type power MOSFET involving a negative voltage protecting circuit which prevents breakdown of an element by restraining a negative direction drain current when a negative voltage is applied to a drain. SOLUTION: In this composite type semiconductor device, a vertical power MOSFET 24 and a vertical power MOSFET 25 are reversely connected in series, a source pad 19 is arranged on the power MOSFET 24, a drain pad 20 is arranged on the power MOSFET 25, and a drain terminal 13, a source terminal 14, a gate terminal 11 and an independent conducting plate 29 whose thickness is greater than or equal to 50μm are arranged on the back of a semiconductor chip 18. In order to facilitate a bonding process, a dummy terminal 12 which is connected to the conducting plate 29 is sealed with mold 30 in the state that the dummy terminal 12 is connected to the drain terminal, the source terminal and the gate terminal, and the dummy terminal 12 is separated from the drain terminal, the source terminal and the gate terminal.

7. 发明专利

JPH08204081A LEAD FRAME FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JPH08204081A
公开(公告)日：1996-08-09
申请号：JP1230095
申请日：1995-01-30
申请人： HITACHI LTD
发明人： ITO KAZUTOSHI , OHASHI TAKEYA , YAMADA TOMIO
IPC分类号： H01L23/48 , H01L23/50
摘要： PURPOSE: To avoid damage of a lead frame for semiconductor device due to defective bonding of a solder layer and Ni plating layer of the lead frame. CONSTITUTION: In production of a lead frame composed of a solder and Ni-P plating layers, the concn. of P in the plating layer is reduced to eliminate the influence of P, the soldering temp. is elevated, or a Ni-plating layer thick enough to prevent P in the Ni-P plating layer from reaching the solder layer due to the diffusion of P during heat treatment is formed on the Ni-P plating layer (P concn. 2wt.% or less). This improves the reliability of the lead frame for semiconductor devices.

8. 发明专利

JPH05102217A SEMICONDUCTOR DEVICE, MANUFACTURE THEREOF AND MOLDING APPARATUS USED THEREFOR 失效
公开(公告)号：JPH05102217A
公开(公告)日：1993-04-23
申请号：JP28362491
申请日：1991-10-02
申请人： HITACHI LTD
发明人： YAMADA TOMIO , HOSHI AKIRO
IPC分类号： H01L21/56 , B29C45/14
摘要： PURPOSE:To provide the molding technique with which both slipping of bonding wire by resin and the vibration of a work in vertical direction can be prevented. CONSTITUTION:A gate 38 is formed in the direction toward the radial center of a wire in a cavity 40, and a press-pin 5 is provided on the opposite side of the gate 38 pinching a work 24 in such a manner that the work 24 is supported. An air vent 46 is perforated around the press-pin 45. Accordingly, as the resin 47, which is press-inserted into the cavity 40 from the gate 38, orthogonally strikes the work 24 and flows in a radial direction along a wire, the sideward falling phenomenon of a wire arch caused by the stream of resin can be prevented. The work 24 is going to be vibrated by the collision against the work 24 of the resin 47, but as the work 24 is pressed by the press-pin 45, the vibration can be prevented. Also, the air of the cavity 40 is expelled completely through an air vent 46.

9. 发明专利

JPH04139749A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04139749A
公开(公告)日：1992-05-13
申请号：JP26057690
申请日：1990-10-01
申请人： HITACHI LTD
发明人： YAMADA TOMIO , YAMAZAKI KAZUO
IPC分类号： H01L23/373 , H01L23/29 , H01L23/31
摘要： PURPOSE:To realize a low thermal resistance while maintaining a predetermined moisture resistance by forming a package of inner and outer layers of two types of resins in a semiconductor device having a resin-sealed package. CONSTITUTION:An inner layer 26 of a resin-sealed package 25 is formed of low stress resin, and its outer layer 27 is formed of high thermal conductivity resin. Accordingly, low thermal resistance can be realized while maintaining moisture resistance. Thus, since a pellet 22, wirings 24, etc., are covered with low stress resin of the layer 26 in a PGA.IC 10 of the above structure, predetermined moisture resistance is obtained, and a stress to be applied to the pellet 22, the wirings 24 is suppressed. When heat generated from the pellet 22 is thermally conducted to the outside layer 27 through the layer 26, it is extremely effectively dissipated out of the package 25 through the layer 27.

10. 发明专利

JPH03242948A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH03242948A
公开(公告)日：1991-10-29
申请号：JP4068090
申请日：1990-02-21
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： TAKAHASHI TOSHIHARU , NAGAMINE TORU , TANBA TSUTOMU , MUTO AKIRA , SHINTANI TOSHIYUKI , HOSHI AKIRO , YAMADA TOMIO , HATORI KAZUO
IPC分类号： H01L23/50 , H01L21/60
摘要： PURPOSE:To promote fabrication of finer chip without using wire bonding technique by joining each communicating wiring of a film to each electrode pad of a semiconductor pellet and the inner part of each lead, respectively, so that they are communicated electrically. CONSTITUTION:An IC 10 having a resin sealing small outline package is provided with a semiconductor pellet 21 wherein an electronic circuit is built, a plurality of leads 7 to lead out the electronic circuit outside electrically and a package 8 to resin-seal an inner part 7a of each lead 7 and a semiconductor pellet 21. A film 18 wherein a plurality of communicating wirings 15 are formed is provided to the inside of the package 8. Each communicating wiring 15 of the film 18 is joined to each electrode pad 23 of the semiconductor pellet 21 and the inner part 7a of each lead 7, respectively, to communicate them electrically. Thereby, it is possible to omit use of wire bonding technique and to make fine a communicating wiring.

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