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1. 发明授权

US5243538B1 Comparison and verification system for logic circuits and method thereof 失效
标题翻译：逻辑电路的比较和验证系统及其方法
公开(公告)号：US5243538B1
公开(公告)日：1995-11-07
申请号：US56349290
申请日：1990-08-07
申请人： HITACHI LTD
发明人： OKUZAWA OSAMU , MATSUMOTO KAZUHIKO , IKARIYA YUKIO , MOCHIZUKI HIROSHI
IPC分类号： G06F11/25 , G06F17/50
CPC分类号： G06F17/504

2. 发明专利

JP2000011017A LOGICAL SIMULATION METHOD 失效
公开(公告)号：JP2000011017A
公开(公告)日：2000-01-14
申请号：JP17076998
申请日：1998-06-18
申请人： HITACHI LTD
发明人： OKUZAWA OSAMU , SUZUKI KAORU
IPC分类号： G01R31/28 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To execute a high-speed instruction level simulation in an instruction level simulator and to correctly simulate a circuit in a logical simulator by providing a flag for judging whether data is the one written by means of the logical simulator or not at the time of reading a parity bit of the data and generating the parity bit only when the flag is invalid. SOLUTION: Logical simulation where a logical simulator 101 is connected to an instruction simulator 105 is provided with a storage element model where a memory area 107 is divided into a data part, a parity bit part and a parity bit flag part. In the instruction simulator 105, reference and writing are executed in the data part, the parity bit part is not used and the parity bit flag part corresponding to the written data is made to be invalid. In the logical simulator 101, the reference and writing are executed in the both of the data part and the parity bit part and the parity bit flag corresponding to the written data is made to be valid.

3. 发明专利

JPS6361354A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPS6361354A
公开(公告)日：1988-03-17
申请号：JP20372286
申请日：1986-09-01
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： UEDA SUSUMU , OKUZAWA OSAMU
IPC分类号： G06F13/36
摘要： PURPOSE:To attain the transmitted mode transmission by applying bit string adding conversion to data on one side transmission system, transmitting as the data even on the other side transmission system and obtaining the necessary data by reverse conversion at a receiving side. CONSTITUTION:At the time of the data transmission between a host 1 transmitting by a non-transmitted mode and a host 2 transmitting by a transmitted mode, a procedure converting device 3 is provided between hosts 1 and 2. the data from the host 2 are first received by the device 3 and by 3 byte 4 byte conversion, the transmitted mode data are converted to the data of the non- transmitted mode. Further, by the procedure in which the transmitted mode transmission is not supported, the transmission is transmitted to the host 1, the received data are converted from 4 byte/3 byte at the host 1, converted to original transmitted data, and by the conversion reverse to the time of receiving, the data are transmitted to the host 2.

4. 发明专利

JP2001331542A LOGIC SIMULATION JOB CONTROL SYSTEM 失效
公开(公告)号：JP2001331542A
公开(公告)日：2001-11-30
申请号：JP2000154378
申请日：2000-05-22
申请人： HITACHI LTD
发明人： IIOKA YUMIKO , OKUZAWA OSAMU , OSONO KATSUMI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To eliminate a waste of computer time at job execution suppression processing by reviewing suppression conditions for suppressing the execution of an unnecessary logic simulation job and to provide a means for easily grasping logic simulation progress states for each test item. SOLUTION: This system is equipped with a means which suppresses following logical simulation job execution if the number of generated defects exceeds a certain value and a means which outputs logic simulation progress information for each test item obtained from a file stored with logic simulation results in the form of a list.

5. 发明专利

JPH06176096A LOGICAL SIMULATION RE-EXECUTING METHOD AND DEVICE THEREFOR 失效
公开(公告)号：JPH06176096A
公开(公告)日：1994-06-24
申请号：JP32911392
申请日：1992-12-09
申请人： HITACHI LTD
发明人： OKUZAWA OSAMU
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50 , G06F15/60
摘要： PURPOSE:To improve the logical simulation efficiency for design of a logic circuit by using the hitherto results as a part of the input data when the logical simulation is repeated during the partial correction of the logic circuit. CONSTITUTION:A partial circuit that can use the result of the precedent simulation is obtained based on a recognized circuit correction range designated by a user. Then the change of the input signal of the partial circuit caused by the precedent simulation is regarded as an input pattern. Then the logical simulation is carried out by a logical simulation re-executing device which consists of a partial circuit recognizing part 103, a reverifying range calculating part 105, a signal connection information file 106, a simulation result file 107, a re-logical simulation control part 110, etc. Thus the logical simulation re- executing device re-verifies a part of a logic circuit.

6. 发明专利

JPH03156572A SYSTEM AND METHOD FOR COMPARING AND VERIFYING LOGIC CIRCUIT 失效
公开(公告)号：JPH03156572A
公开(公告)日：1991-07-04
申请号：JP20807590
申请日：1990-08-08
申请人： HITACHI LTD
发明人： OKUZAWA OSAMU , MATSUMOTO KAZUHIKO , IKARIYA YUKIO , MOCHIZUKI HIROSHI
IPC分类号： G06F11/25 , G06F17/50
摘要： PURPOSE:To make a decision by one time processing without a loop by executing simplification and afterwards, coupling the parts of common structure from a lower layer part by two prepared binary determination trees (BDD) when deciding equivalency to the two BDD. CONSTITUTION:For each logic at a higher level and a lower level, a logic circuit, true value table or Boolean formulas 1 and 2 are transformed to Boolean formulas 3 and 4. In a BDD preparation part, development by adapting a Shannon's formula to the Boolean formulas 3 and 4 is executed with the same order of a variable to be round off and BDD 5 and 6 are respectively prepared. Afterwards, the BDD are simplified by a BDD simplification part 12 and the both BDD are compared by a BDD comparison part 13.

7. 发明专利

JPH10260945A PARALLEL COMPUTER SYSTEM USING NETWORK 失效
公开(公告)号：JPH10260945A
公开(公告)日：1998-09-29
申请号：JP8611797
申请日：1997-03-19
申请人： HITACHI LTD
发明人： ISHIBASHI NORIKO , KUROSAKI MASATO , OKUZAWA OSAMU
IPC分类号： G06F15/16 , G06F9/52 , G06F15/163 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To facilitate an analysis, etc., when a network failure occurs by providing a means which stores receiving packet information that is stored in a packet information storage area for receiving packets and transit node information that is stored in a transit node information storage area in a receiving packet information storage area. SOLUTION: A transit node information storing part 126 stores a packet transit time and self node position information in a transit node information storage area in a transit packet. A receiving packet information storing part 127 stores packet information of a receiving packet and all transit node information in a receiving packet information storage area in a self node when the packet of a sending packet is received in a destination packet of the sending packet. Further, a packet information storage area 133 stores packet information that consists of sending time information at which a packet is sent, sending node position information and destination node position information. A transit node information storage area 134 stores packet transit time, etc., of entire nodes.

8. 发明专利

JPH09223168A LOGIC SIMULATION MODEL METHOD 失效
公开(公告)号：JPH09223168A
公开(公告)日：1997-08-26
申请号：JP3032896
申请日：1996-02-19
申请人： HITACHI LTD
发明人： OKUZAWA OSAMU , KINOSHITA YOSHIAKI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To enable fast processing at simulation execution time by taking an analysis while regarding delay less than a certain delay value as 0 in a circuit as an object of logic simulation and generating a file for simulation. SOLUTION: A logic description 101 of the circuit as the object of logic simulation is read by a logic description input part 103. The restrictions and a specific value 102 at the time of the analysis are read in by a restriction and specific value input part 104. Then a logic description conversion part 105 analyzes the logic description according to the read-in restrictions and specific value. Namely, each execution statement (process) of the logic description is scanned and its delay value is compared with a specific delay value; when the delay value is less, the delay value in the logic description is rewritten to 0. Then the logic description is analyzed and data for simulation are outputted to the file.

9. 发明专利

JPH11282889A Logic circuit data processing method 失效
标题翻译：逻辑电路数据处理方法
公开(公告)号：JPH11282889A
公开(公告)日：1999-10-15
申请号：JP7949998
申请日：1998-03-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUKISHIRO KENICHI , OKUZAWA OSAMU
IPC分类号： G06F17/50 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To efficiently use a CAD system for verification of a logic circuit by minimizing consumption of a memory to be required for storing logic circuit information.
SOLUTION: Processings are divided into a pre-processing 107 to create a table in which structure and connection information of all circuits are described and to process the table and main verification processing 110 by the CAD system itself in the logic circuit to be formed as hierarchical structure. And the processings are efficiently performed by replacing all signal names to be extended over hierarchy with one representative name, further compressing names and the signal names to be used as a block identifier of each hierarchy from the names with variable length into short names with fixed length in the pre-processing and minimizing data quantity and the consumption of the memory in the main processing 110.
COPYRIGHT: (C)1999,JPO
摘要翻译：要解决的问题：通过最小化存储逻辑电路信息所需的存储器的消耗来有效地使用CAD系统来验证逻辑电路。解决方案：将处理分为预处理107以创建其中描述所有电路的结构和连接信息的表格，并且通过CAD系统本身在逻辑电路中处理表和主验证处理110以形成分层结构体。并且通过用一个代表名替换要在层次结构上扩展的所有信号名称，并且将具有可变长度的名称用作具有固定长度的短名称的每个层级的块标识符的名称和信号名称在主处理110中的预处理和最小化数据量和存储器的消耗。

10. 发明专利

JPH09269954A METHOD FOR GENERATING LOGICAL SIMULATION MODEL 失效
公开(公告)号：JPH09269954A
公开(公告)日：1997-10-14
申请号：JP7899996
申请日：1996-04-01
申请人： HITACHI LTD
发明人： SUGIMOTO ICHIRO , OKUZAWA OSAMU , ITO MASAKI , TOMITA HIROSHI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To generate simulation data where the partial circuit of an event evaluation unit is connected to be a size suitable for execution by judging whether or not the respective partial circuits are the combined ones and integrating the partial circuits being the combined ones so as to adopt them as one event evaluation unit. SOLUTION: A process judging part 104 judges whether or not respective processes added in an object logical circuit are the combined ones and adopts the processes satisfying a condition as order circuits and the other ones as the combined ones. An order circuit process integration evaluating part 105 extracts the process where a control signal is equal as an integration object concerning the circuits adopted as the order ones. A combined circuit process integration evaluating part 106 executes calculation concerning the circuits adopted as the combined ones and decides the process to be integrated. A process integrating part 107 integrates the processes which become the integration object and generates logical circuit connecting information 108 and a data output part 109 generates a logical simulation model 110 based on it.

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