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1. 发明专利

JPH0896021A LOGICAL SIMULATION DEVICE FOR PARALLEL PROCESSOR 失效
公开(公告)号：JPH0896021A
公开(公告)日：1996-04-12
申请号：JP23278594
申请日：1994-09-28
申请人： HITACHI LTD
发明人： SUZUKI KAORU , NAKAYAMA KAZUE , YONEYAMA SHUJI
IPC分类号： G06F11/25 , G06F17/50
摘要： PURPOSE: To attain the fast and effective logical simulation of a parallel processor system of a large scale regardless of the logical mounting limitation of a circuit simulator by simulating a processor control logic part by an instruction interpreter and using the circuit simulator to simulate the network logic only. CONSTITUTION: The logical simulation device simulates the parallel processors which are connected together by a network and is provided with a circuit simulator 202 which simulates a network logic part and a network control logic part at a gate level, an instruction interpreter 205 which simulates a processor control logic part at a data transfer function level, a process scheduler 201 which controls the simulator 202 and the interpreter 205 by occurrence of an event, a 1st storage part which stores the registered network constitution information and receives an access from the scheduler 201, and a 2nd storage part which stores the registered each processor unit information and is managed by the interpreter 205.

2. 发明专利

JPH07253909A MICROPROGRAM VERIFYING METHOD 失效
公开(公告)号：JPH07253909A
公开(公告)日：1995-10-03
申请号：JP4530894
申请日：1994-03-16
申请人： HITACHI LTD , HITACHI COMPUTER ELECTRONIC , HITACHI COMPUTER ENG
发明人： SOMEYA SATORU , NAKAMURA AYUMI , TANAKA JUNKO , SUZUKI KAORU , MORI SHIGERU , NOMURA NOBUYUKI , RYUMON MASAKI
IPC分类号： G06F11/28 , G06F9/22
摘要： PURPOSE:To verify a general purpose microprogram which does not depend upon the specifications of a computer system. CONSTITUTION:A compiler 8 automatically generates various information files 9-14 from a specifications information file 7 described according to a microprogram specification description language file 6. A microinstruction simulator 1 after setting test environment with the information files 10 and 13 executes the microprogram 5 to be verified by simulation in source step units on the basis of the information files 9, 11, 12, etc., and gathers the execution results in a file 17. A specifications limitation checker 3 verifies violation with microinstruction specifications limitation information as to the execution results. An architecture simulator 2 simulates the architecture of the object computer system on a function level.

3. 发明专利

JPH0784821A TEST SYSTEM FOR CONFLICT OPERATION OF PARALLEL PROCESSOR 失效
公开(公告)号：JPH0784821A
公开(公告)日：1995-03-31
申请号：JP23166493
申请日：1993-09-17
申请人： HITACHI LTD
发明人： SUZUKI KAORU
IPC分类号： G06F11/22 , G06F13/00
摘要： PURPOSE:To make logic verification highly precise and efficient by transferring sent and received data of test packets to other processor units according to test information in the packet header. CONSTITUTION:A network transmitter receiver C107, when recognizing that a received packet is the test packet from the packet identifier of the packet header of the received packet, rewrites the transmission source processor address (b) in the packet header into its processor address (c) and the transmission destination processor address into a transmission destination processor address (a) registered in the entry right after its processor address (c) in the packet header, and sends the test packet according to a corresponding transmission kind. In this case, the received test packet is sent to a processor unit A101 as a test communication start processor. This test packet is returned to the test start processor (processor unit A101) eventually through the network transmitter receiver on a network.

4. 发明专利

JPH06282599A LOGIC VERIFYING METHOD AND DEVICE 失效
公开(公告)号：JPH06282599A
公开(公告)日：1994-10-07
申请号：JP6796693
申请日：1993-03-26
申请人： HITACHI LTD
发明人： SUZUKI KAORU , OSAKABE KEISUKE
IPC分类号： G01R31/28 , G06F11/25 , G06F11/26 , G06F11/32 , G06F17/50 , G06F15/60
摘要： PURPOSE:To highly precisely and efficiently execute wide logic verification which is not restrained by an executing environment, and to easily realize fault analysis at the time of the occurrence of a fault. CONSTITUTION:Logic circuit constitution information at the plural arbitrary spots of an arbitrary program to be executed is registered in a file on an instruction interpreter 102 which simulates a logic verifying operation equivalent to a logic circuit device or a circuit simulator in a data transfer level, and the content of the file is used as an initial value at the arbitrary spot when the program is executed, or used as an expected value when the program is executed until the other arbitrary spot. Then, only the arbitrary section of the program is executed, and the right and wring of the result is discriminated.

5. 发明专利

JPH06231201A LOGICAL VERIFICATION ENVIRONMENT SETTING DEVICE 失效
公开(公告)号：JPH06231201A
公开(公告)日：1994-08-19
申请号：JP1441793
申请日：1993-02-01
申请人： HITACHI LTD
发明人： SUZUKI KAORU , SUGANO KOJI
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50 , G06F15/60
摘要： PURPOSE:To execute a logical verification of higher precision by constructing the same logical simulation environment as the case of executing the logical verification under a real computer system. CONSTITUTION:When a logical verification program executed by a logical simulation device 101 is finished, a data saving device 105 reads out a state of a register, a memory, etc., and stores it in a file 103. When execution of the next logical verification program is started, a data re-setting device 106 reads out the previous saved data from the file 103, re-sets it to the register, the memory, etc., and executes continuously a logical simulation.

6. 发明专利

JPH03116245A MEASURING DEVICE FOR INSTRUCTION PERFORMANCE 失效
公开(公告)号：JPH03116245A
公开(公告)日：1991-05-17
申请号：JP25500289
申请日：1989-09-28
申请人： HITACHI LTD
发明人： SUZUKI KAORU , HIROSE ZENTARO , SHINTANI YOICHI , SUGIYAMA ATSUSHI
IPC分类号： G06F11/26
摘要： PURPOSE:To measure the instruction performance via a logical simulator in a short time and with the satisfactorily high accuracy by providing a cycle counter mechanism which updates a cycle counter included in a pseudo local storage every +1. CONSTITUTION:A measurement environment setting mechanism 120 reads the measurement data out of measurement subject data file 150 and starts a logical simulator 110 after setting an instruction train, the register data, an address, etc., to a pseudo memory 100. A cycle counter mechanism 130 extract a clock signal T0 out of a clock mechanism of a logical simulator and updates a cycle counter 102 included in a pseudo local storage 101 every +1. A measurement result calculating/editing output mechanism 140 calculates the executing cycle number for an instruction to be measured from the cycle counter value and edits the calculation result to output it to a printer, a result file, or a terminal console 160. As a result, the instruction performance of the logical simulator is measured at a high speed since no loop execution is required.

7. 发明专利

JPS6412344A SYSTEM FOR MEASURING PERFORMANCE OF MULTIPROCESSOR 失效
公开(公告)号：JPS6412344A
公开(公告)日：1989-01-17
申请号：JP16843887
申请日：1987-07-06
申请人： HITACHI LTD
发明人： SUZUKI KAORU
IPC分类号： G06F11/34 , G06F15/16 , G06F15/177
摘要： PURPOSE:To measure performance characteristics in a various kinds of states, by setting environment by a processor on a slave side, and generating the competitive state of a processing falsely at the time of measuring the processing time of an instruction by the processor on a master side. CONSTITUTION:A measuring object instruction and measuring environment information are accumulated in a data accumulation part 11 for measurement. A state control part 12 on the master side controls the initialization of the processors 3-1 and 3-2 and the operations of a performance measurement part 13 and an environment setting part 15 based on information extracted from the data accumulation part 11. The performance measurement part 13 issues the measuring object instruction, and measures the processing time. Synchronizing with the above operation, the environment setting part 15 in a slave instruction processor issues a read/write instruction to a storage area in a memory device 1 to which an object instruction makes access, and generates a false competitive state. After the measurement is completed, control is delivered to an edit output part 14, and a measured result is outputted.

8. 发明专利

JPS6365543A MEASURING SYSTEM FOR INSTRUCTION PERFORMANCE 失效
公开(公告)号：JPS6365543A
公开(公告)日：1988-03-24
申请号：JP20949686
申请日：1986-09-08
申请人： HITACHI LTD
发明人： SUZUKI KAORU
IPC分类号： G06F11/34 , G06F9/38
摘要： PURPOSE:To attain measurement with high accuracy, by arranging an environmental installation instruction group around an instruction to be measured, and using a carry method at the time of calculating the execution time of the instruction. CONSTITUTION:A pair of an initialization instruction and the environmental installation instruction group 1, and the instruction to be measured and a following environmental installation instruction group 2, is formed, and the pair of those instructions is executed repeatedly for N-times by a branching instruction. The execution start time Ts1 and the completion time Te1 of a first routine are read by a timepiece mechanism, and the execution time is given as (Te1-Ts1). In a second routine, the initialization instruction and the environmental installation instruction groups 1 and 2, and the branching instructions for N-times except the instruction to be measured on which a bracket ( ) is attached, are executed, and an execution start time Ts2 and a completion time Te2 are read, and the execution time is given as (Te2-Ts2). A time required for N-times of execution of the instruction to be measured is (Te1-Ts1)-(Te2-Ts2). At time of finding a solution by dividing a value by N, a figure below the figure desired to obtain is rounded off.

9. 发明专利

JP2009005212A Network apparatus, program, and power supply control method 审中-公开
标题翻译：网络设备，程序和电源控制方法
公开(公告)号：JP2009005212A
公开(公告)日：2009-01-08
申请号：JP2007165890
申请日：2007-06-25
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HORI SATORU , FUJIOKA TAKAYOSHI , SAMEJIMA SHIGETOSHI , SUZUKI KAORU
IPC分类号： H04W84/12 , H04W24/00 , H04W52/02
CPC分类号： Y02D70/00
摘要： PROBLEM TO BE SOLVED: To provide a technique for reducing consumed electric power by autonomously performing power supply control in a network apparatus without imparting any change to a partner side of communication.
SOLUTION: A rule storage region 135a stores conditions corresponding to communication data and processings corresponding to the conditions in correspondence. A communication data judgement part 136b and a power supply control part 136c perform the processings corresponding to the conditions when communication data transmitted and received via a network module 132 satisfy the conditions.
COPYRIGHT: (C)2009,JPO&INPIT

10. 发明专利

JP2005182108A Electronic card reference system and medical examination history information leakage preventing filing system and electronic card reference method 审中-公开
标题翻译：电子卡参考系统和医学检查历史信息防漏填充系统和电子卡参考方法
公开(公告)号：JP2005182108A
公开(公告)日：2005-07-07
申请号：JP2003417564
申请日：2003-12-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HOSOKAWA NAGANORI , SUZUKI KAORU , SUGAWA YOKO
IPC分类号： G09C1/00 , G06Q50/22 , G06Q50/24 , G06F17/60
摘要： PROBLEM TO BE SOLVED: To make it necessary to limit the information of an electronic card file to be disclosed to any person other than a patient according to the contents of medical examination activities even when the person is responsible for the medical examination, and to make it necessary to provide a mechanism for preventing the patient from being specified even when the electronic card file is illegally leaked to the outside. SOLUTION: In an electronic card reference system server system 6, a file does not include any patient basic information but includes an encrypted XML file 4 obtained by encrypting a file having the file name of random numbers by using a secret key for each of the attributes of reference authority and an XML file association table 13 and a secret key. Thus, it is possible to limit files to which a user who operates a client 8 can refer, and to prevent any patient from being specified only by the file. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使在负责体检的情况下，有必要根据体格检查活动的内容，将要发布的电子卡片文件的信息限制在患者以外的任何人身上，并且使得有必要提供即使当电子卡文件非法泄漏到外部时也防止指定患者的机构。解决方案：在电子卡参考系统服务器系统6中，文件不包括任何患者基本信息，但是包括通过使用每个的秘密密钥加密具有随机数的文件名的文件而获得的加密的XML文件4 参考权限的属性和XML文件关联表13和秘密密钥。因此，可以限制操作客户端8的用户可以引用的文件，并且防止仅由该文件指定任何患者。版权所有（C）2005，JPO＆NCIPI

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