专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2010146037A Logic verification system 审中-公开
标题翻译：逻辑验证系统
公开(公告)号：JP2010146037A
公开(公告)日：2010-07-01
申请号：JP2008319078
申请日：2008-12-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OSONO KATSUMI
IPC分类号： G06F17/50 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To solve the following problem of cooperation verification between hardware and software: logic verification takes a very long time because a lot of test data are processed in a logic simulator or an emulator so as to execute the software, and re-execution of a test also takes a lot of time when the hardware or the software are changed, so that they cause verification period extension. SOLUTION: The hardware and software cooperation verification system efficiently executes the test by outputting coverage information of the hardware and the software when executing the cooperation verification of the hardware and the software, classifying a test case wherein the coverage information changes and a test case wherein it does not change, accumulating only the test cases wherein the coverage information is improved, and using them when re-executing the test. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：解决硬件与软件之间的合作验证的以下问题：逻辑验证需要很长时间，因为在逻辑模拟器或仿真器中处理大量测试数据以执行软件，当硬件或软件更改时，重新执行测试也需要很多时间，从而导致验证期延长。解决方案：硬件和软件协作验证系统在执行硬件和软件的合作验证时，通过输出硬件和软件的覆盖信息来有效地执行测试，对覆盖信息进行更改的测试用例进行分类和测试其中不改变的情况，仅积累覆盖信息被改进的测试用例，并且在重新执行测试时使用它们。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009205239A Software verification system 审中-公开
标题翻译：软件验证系统
公开(公告)号：JP2009205239A
公开(公告)日：2009-09-10
申请号：JP2008044261
申请日：2008-02-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OSONO KATSUMI
IPC分类号： G06F11/28
摘要： PROBLEM TO BE SOLVED: To develop a high-quality product in a short term by analyzing change points in a module and automatically executing a test case and a test with an expectation value changed.
SOLUTION: By analyzing a source code to be tested, a change in an input/output interface can be reflected, and input-related information including an input value (test case) and an output value (expectation value) or input/output relationship information after the change is created. By using the created input-related information or the input/output relationship information after the change, the test case or the test case after the change is created. Then, the test is executed by the test case or the test case after the change, and the expectation value or the expectation value after the change.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过分析模块中的变更点并自动执行测试用例和期望值更改的测试，在短期内开发高质量的产品。
解决方案：通过分析要测试的源代码，可以反映输入/输出接口的变化，输入相关信息包括输入值（测试用例）和输出值（期望值）或输入/ 创建更改后的输出关系信息。通过使用创建的输入相关信息或更改后的输入/输出关系信息，创建变更后的测试用例或测试用例。然后，测试由测试用例或更改后的测试用例执行，更改后的期望值或期望值。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2008171158A Software and hardware cooperation verification system 审中-公开
标题翻译：软件和硬件合作验证系统
公开(公告)号：JP2008171158A
公开(公告)日：2008-07-24
申请号：JP2007002941
申请日：2007-01-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： OSONO KATSUMI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To achieve a hardware model at low costs by installing an interface automatic generation part for automatically generating the model of an interface section based on the designation of a parameter file.
SOLUTION: In this system, an interface automatic generation part 201 is provided with a function for integrating the configuration control part of the hardware model of a peripheral device into a software model, and for automatically generating a timing control and interface model section. Thus, it is possible to efficiently prepare a hardware model.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过安装用于根据参数文件的指定自动生成接口部分的模型的接口自动生成部件，以低成本实现硬件模型。解决方案：在该系统中，接口自动生成部201具有将外围设备的硬件模型的配置控制部分整合为软件模型的功能，并且用于自动生成定时控制和接口模型部分。因此，可以有效地制备硬件模型。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2001331542A LOGIC SIMULATION JOB CONTROL SYSTEM 失效
公开(公告)号：JP2001331542A
公开(公告)日：2001-11-30
申请号：JP2000154378
申请日：2000-05-22
申请人： HITACHI LTD
发明人： IIOKA YUMIKO , OKUZAWA OSAMU , OSONO KATSUMI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To eliminate a waste of computer time at job execution suppression processing by reviewing suppression conditions for suppressing the execution of an unnecessary logic simulation job and to provide a means for easily grasping logic simulation progress states for each test item. SOLUTION: This system is equipped with a means which suppresses following logical simulation job execution if the number of generated defects exceeds a certain value and a means which outputs logic simulation progress information for each test item obtained from a file stored with logic simulation results in the form of a list.

5. 发明专利

JP2002041593A METHOD FOR PREPARING PSEUDO LOGIC MODEL 失效
公开(公告)号：JP2002041593A
公开(公告)日：2002-02-08
申请号：JP2000226183
申请日：2000-07-21
申请人： HITACHI LTD
发明人： OSONO KATSUMI
IPC分类号： G01R31/28 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To make usable pseudo logic model, which is prepared by using a program language, for a different logic simulator or different logic circuit configuration without changing the description thereof. SOLUTION: Pseudo logic models 101 and 103 are made into an object by using an object-oriented language such as C++ language and the preparation of the object of the pseudo logic model matching with the number of verification object LSI 102 is automated. Concerning a configuration 2, since the number of verification object LSI becomes two, a logic circuit configuration is previously described in a setting file and by using a connection controller prepared from the description in the setting file, the object of the pseudo logic model is automatically prepared. Thus, the pseudo logic model, which can be operated even when the logic configuration is changed, is provided and the preparation of a logic simulation environment in the different logic circuit configuration is facilitated.

6. 发明专利

JP2000259684A PARALLELED LOGICAL SIMULATOR SYSTEM 失效
公开(公告)号：JP2000259684A
公开(公告)日：2000-09-22
申请号：JP5733399
申请日：1999-03-04
申请人： HITACHI LTD
发明人： OSONO KATSUMI , TOMITA HIROSHI , MIZUGUCHI HIROSHI
IPC分类号： G06F17/50 , G06F11/25 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To provide a paralleled logical simulator capable of quickly executing the simulation of electric characteristics of a logical circuit by dividing the circuit. SOLUTION: The paralleled logical simulator for executing the preprocessing of simulation at high speed by paralleling the development processing of a logical circuit model 201 provides the logical circuit model 201 and a division definition file 202 including the information of dividing positions of logical circuits to an optional computer 103. While executing the development processing of the model 201, the computer 103 searches the dividing positions of the circuits, and at the time of recognizing dividing positions 201a to 201c, the connection information of the logical circuits on respective dividing positions is prepared and transferred to computers 103 to 106 to which logical circuits after the dividing positions are allocated and the computers 103 to 106 receiving the information execute the development processing of the allocated logical circuits in parallel.

7. 发明专利

JPH1153424A LOGIC SIMULATOR 失效
公开(公告)号：JPH1153424A
公开(公告)日：1999-02-26
申请号：JP22197097
申请日：1997-08-04
申请人： HITACHI LTD
发明人： OSONO KATSUMI , ITO MASAKI , YAMAGATA MAKOTO
IPC分类号： G06F11/25 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To reduce unnecessary inter-node communication by stopping data transmission on a transmission side as to data that are not necessary on a reception side when inter-node communication is carried out. SOLUTION: Logic data 101 is divided into nodes 105 and 107 and simulation is performed. Division information for circuit division is described previously in a division definition file 102 and a circuit dividing process part 103 distributes the logic data to nodes where it is drawn. An event deletion logic insertion part 104 extracts a memory element (flip-flop) having an enable signal, decides a memory element to which a data signal is sent form another node, propagates the enable signal, and inserts event deletion logic. In this case, when conditions indicate no need, the transmission of the data to the reception-side node is suppressed. Further, a communication control part 106 allows communication between nodes if an event occurs to a signal connecting the nodes at the time of simulation execution.

8. 发明专利

JPH07295870A HISTORY MANAGEMENT METHOD FOR DATA BASE FILE 失效
公开(公告)号：JPH07295870A
公开(公告)日：1995-11-10
申请号：JP11206594
申请日：1994-04-27
申请人： HITACHI LTD , HITACHI SOFTWARE ENG
发明人： OSONO KATSUMI , TSUGE HIROSHI
IPC分类号： G06F12/00
摘要： PURPOSE:To attain the accurate management of history of a data base file which contains the binary data and the text data in a mixed manner, and besides, to eliminate the shortage of capacity of a hard disk. CONSTITUTION:When a DB(data base) file of both T(text) and B(binary) data is updated to a VERn+1 (version n+1) file 103, the B data of the file 103 is converted into the T data based on (104) a record structure description file 105 for generation of a T file 106 of the file 103. Then a VERn+1 differential file 107 is generated based on the file 106 and a VERn differential file 102 of an external memory. When a file of an old version is designated and its regeneration is instructed, the file 106 of the designated version is regenerated (109) through the designation of an oil version file and differential file. Then the file 106 is reversely converted into a T&B-DB file (110) based on the file 105.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式