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1. 发明专利

DE69528798T2 未知
公开(公告)号：DE69528798T2
公开(公告)日：2003-08-14
申请号：DE69528798
申请日：1995-06-23
申请人： HITACHI LTD
发明人： KAWAGOE HIROTO , SHIRASU TATSUMI , KIYOTA SHOGO , SUZUKI NORIO , YAMADA EIICHI , SUGINO YUJI , KITANO MANABU , SAKURAI YOSHIHIKO , NAGANUMA TAKASHI , ARAKAWA HISASHI
IPC分类号： H01L29/78 , H01L21/205 , H01L21/8238 , H01L27/092
摘要： Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

2. 发明专利

DE69528798D1 未知
公开(公告)号：DE69528798D1
公开(公告)日：2002-12-19
申请号：DE69528798
申请日：1995-06-23
申请人： HITACHI LTD
发明人： KAWAGOE HIROTO , SHIRASU TATSUMI , KIYOTA SHOGO , SUZUKI NORIO , YAMADA EIICHI , SUGINO YUJI , KITANO MANABU , SAKURAI YOSHIHIKO , NAGANUMA TAKASHI , ARAKAWA HISASHI
IPC分类号： H01L29/78 , H01L21/205 , H01L21/8238 , H01L27/092
摘要： Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

3. 发明专利

HK1010768A1 CMOS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 未知
公开(公告)号：HK1010768A1
公开(公告)日：1999-06-25
申请号：HK98111663
申请日：1998-10-30
申请人： HITACHI LTD
发明人： KAWAGOE HIROTO , SHIRASU TATSUMI , KIYOTA SHOGO , SUZUKI NORIO , YAMADA EIICHI , SUGINO YUJI , KITANO MANABU , SAKURAI YOSHIHIKO , NAGANUMA TAKASHI , ARAKAWA HISASHI
IPC分类号： H01L29/78 , H01L21/205 , H01L21/8238 , H01L27/092 , H01L
摘要： Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

4. 发明专利

SG70082A1 Semiconductor integrated circuit device and process for manufacturing the same 未知
公开(公告)号：SG70082A1
公开(公告)日：2000-01-25
申请号：SG1998001015
申请日：1995-12-07
申请人： HITACHI LTD
发明人： SUZUKI NORIO , KIYOTA SHOGO , KUBO MASAHARU , OKUYAMA KOUSUKE , SHIRASU TATSUMI
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792

5. 发明专利

SG34323A1 Semiconductor integrated circuit device and process for manufacturing the same 未知
公开(公告)号：SG34323A1
公开(公告)日：1996-12-06
申请号：SG1995002061
申请日：1995-12-07
申请人： HITACHI LTD
发明人： OKUYAMA KOUSUKE , KUBO MASAHARU , SUZUKI NORIO , KIYOTA SHOGO , SHIRASU TATSUMI
IPC分类号： H01L27/092 , H01L29/78

6. 发明专利

JPH08213478A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08213478A
公开(公告)日：1996-08-20
申请号：JP8231595
申请日：1995-04-07
申请人： HITACHI LTD
发明人： SHIRASU TATSUMI , KIYOTA SHOGO , KUBO SEIJI , OKUYAMA KOSUKE , SUZUKI NORIO
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/205
摘要： PURPOSE: To improve setting accuracy in element characteristics by forming a specified element on an epitaxial layer of a low impurity concentration provided on the first and second semiconductor areas of high impurity concentration. CONSTITUTION: On wells 3a and 3b of high impurity concentration, an epitaxial layer 2E of low impurity concentration is provided, and on the epitaxial layers 2E1 and 2E2. pMOS5P and nMOS5N are formed. Into the epitaxial layer 2E1 on the well 3a, for example, phosphorus of n-type impurity, is introduced. Into the epitaxial layer 2E2 on the well 3b, for example, boron of p-type impurity, is introduced. By this, characteristics of the pNOS 5P and nMOS 5N (threshold voltage, substrate effect, etc.) are set with high accuracy without affected by impurities of the wells 3a and 3b and a semiconductor substrate body 2S, so setting accuracy of the characteristics is improved.

7. 发明专利

JPH0897163A SEMICONDUCTOR WAFER, MANUFACTURE THEREOF, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0897163A
公开(公告)日：1996-04-12
申请号：JP26552994
申请日：1994-10-28
申请人： HITACHI LTD
发明人： KAWAGOE HIROHITO , SHIRASU TATSUMI , KIYOTA SHOGO , SUZUKI NORIO , YAMADA EIICHI , SUGINO YUSHI , KITANO MANABU , SAKURAI YOSHIHIKO , NAGANUMA TAKASHI , ARAKAWA HISASHI
IPC分类号： H01L29/78 , H01L21/205 , H01L21/8238 , H01L27/092
摘要： PURPOSE: To improve the performance and reliability of semiconductor integrated circuit devices and reduce their cost. CONSTITUTION: On the major surface of a semiconductor substrate body 2S containing impurities of a specified conductivity type, an epitaxial layer 2E is formed which contains impurities that have the same conductivity type that the substrate's impurities do and have the same concentration as the design concentration of the substrate's impurities. Thereafter, the gate insulating films 4Nc, 4Pc of MOS FETs 4N, 4P are formed on the epitaxial layer 2E.

8. 发明专利

JPS6129125A Coating device 失效
标题翻译：涂装装置
公开(公告)号：JPS6129125A
公开(公告)日：1986-02-10
申请号：JP14949384
申请日：1984-07-20
申请人： Hitachi Ltd
发明人： KIYOTA SHOGO , KOTANI TETSUJIRO
IPC分类号： B05C11/08 , G03F7/16 , H01L21/027 , H01L21/30
摘要： PURPOSE: To improve the uniformity of the thickness of a coating film formed on the surface of a material to be coated by leading vapor of a solvent to a coating unit by a tube, and evacuating the unit by evacuating means.
CONSTITUTION: Exhaust pumps 5A, 5B are operated to evacuate a coating cup 1, and conveying gas is supplied from a nozzle 12B of a bubbler 12. The gas which passes a thinner 11 contains thinner vapor to pass a feed tube 6 into the coating cup 1. The prescribed amount of photoresist is dropped from the center of a rotating wafer 3 from the end of a nozzle 8, dispersed to the surface of the wafer 3 by centrifugal force to form a coating film of the photoresist. The photoresist scattered from the periphery of the wafer 3 by the centrifugal force is rapidly removed externally of the cup 1 by downward gas stream.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过管将通过溶剂的引导蒸气在被涂覆材料的表面上形成的涂膜的厚度的均匀性提高到通过管排出涂布单元，并且通过抽真空装置抽空该单元。构成：排气泵5A，5B被操作以抽出涂覆杯1，并且从鼓泡器12的喷嘴12B供给输送气体。通过较薄的气体11的气体含有较薄的蒸气以将进料管6通过涂覆杯规定量的光致抗蚀剂从旋转晶片3的中心从喷嘴8的端部落下，通过离心力分散到晶片3的表面，形成光致抗蚀剂的涂膜。通过离心力从晶片3的周边散射的光致抗蚀剂通过向下的气流快速地从杯1的外部除去。

9. 发明专利

JP2001111011A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2001111011A
公开(公告)日：2001-04-20
申请号：JP28595399
申请日：1999-10-06
申请人： HITACHI LTD
发明人： NISHIMOTO TOSHIAKI , AOYANAGI TAKASHI , KIYOTA SHOGO
IPC分类号： G11C16/04 , H01L21/322 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To reduce a dislocation defect and joint leak of a non-volatile memory where a stripe-like element separation region is formed for higher integration, for raised reliability and yield. SOLUTION: An AND type flush memory is formed on a substrate where a stripe-like element separation region 5 is formed while an active region L sandwiched between element separation regions 5 is formed in stripe as well. Here, a silicon single crystal substrate comprising nitrogen or carbon is used as a semiconductor substrate.

10. 发明专利

JPH10209170A SEMICONDUCTOR WAFER, ITS MANUFACTURE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ITS MANUFACTURE 失效
公开(公告)号：JPH10209170A
公开(公告)日：1998-08-07
申请号：JP700697
申请日：1997-01-17
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI NORIO , KIYOTA SHOGO , SHIMIZU HIROBUMI , SAITOU SHIGEAKI , SATO TOMOMI , MATSUDA YASUSHI , SUGINO YUSHI , TANAKA TOSHIHIDE , ISOMAE SEIICHI , TAKEDA KAZUO , ISHIHARA TETSUYA
IPC分类号： H01L21/8247 , H01L21/205 , H01L21/322 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/088 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide an epitaxial wafer for MIS devices at a low cost which has an improved gettering power and gate oxide film characteristics (GOI). SOLUTION: An epitaxial wafer having an epitaxial layer grown on a main surface of a single crystal Si wafer made by the Czochralski method has a microdefect density of 1×10 to 1×10 defects/cm as an epitaxially grown single crystal Si wafer. The epitaxial layer is 0.3-3μm thick, and contains an impurity boron of the same conductivity type less than 3×10 atoms/cm as that of the single crystal Si wafer 1.

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