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1. 发明授权

US3688165A Field effect semiconductor devices 失效
标题翻译：场效应半导体器件
公开(公告)号：US3688165A
公开(公告)日：1972-08-29
申请号：US3688165D
申请日：1970-08-26
申请人： HITACHI LTD
发明人： TOMINAGA YOSHIO , KAWAGOE HIROTO , TERANISHI YUICHI
IPC分类号： H01L29/78 , H01L21/60 , H01L21/78 , H01L27/06 , H01L29/00 , H01L11/14
CPC分类号： H01L24/85 , H01L21/78 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L27/0629 , H01L29/00 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/49171 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01039 , H01L2924/01078 , H01L2924/01322 , H01L2924/014 , H01L2924/12036 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2224/05556 , H01L2224/05599 , H01L2224/85399
摘要： A semiconductor device in which, for example, an insulated gate type field effect transistor is formed in a major surface of an N-type silicon substrate having an edge that is formed by mechanical separation; a P-type region is formed in a portion of the edge area of the substrate or in the entire edge area of the substrate, and a metal electrode for grounding is connected to the P-type region.
摘要翻译：一种半导体器件，其中例如绝缘栅型场效应晶体管形成在具有通过机械分离形成的边缘的N型硅衬底的主表面上; 在基板的边缘区域的一部分或基板的整个边缘区域中形成P型区域，并且用于接地的金属电极连接到P型区域。

2. 发明授权

US3623217A Method of manufacturing a field effect semiconductor device 失效
标题翻译：制造场效应半导体器件的方法
公开(公告)号：US3623217A
公开(公告)日：1971-11-30
申请号：US3623217D
申请日：1969-11-26
申请人： HITACHI LTD
发明人： KAWAGOE HIROTO , KUBO MASAHARU
IPC分类号： H01L21/316 , H01L27/07 , H01L29/00 , B01J17/00 , H01G13/00
CPC分类号： H01L27/0733 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/02263 , H01L21/31612 , H01L29/00
摘要： A METHOD OF MANUFACTURING AN MIS TYPE FET, WHEREIN, AFTER SOURCE AND DRAIN REGIONS ARE FORMED IN A SURFACE OF A SEMICONDUCTOR BODY, A PART OF AN INSULATING FILM WHICH HAS BEEN USED AS A SELECTIVE DIFFUSION MASK IS REMOVED TO EXPOSE A CARRIER PATH BETWEEN THE REGIONS AND A CONTINUOUS PART OF THE SOURCE REGION, WHILE THE OTHER PART OF THE INSULATING FILM COVERING THE SEMICONDUCTOR SURFACE, ESPECIALLY, THE SURFACE PORTION OF THE DRAIN REGION ADJACENT TO THE CARRIER PATH IS LEFT, THEN THE EXPOSED SURFACE OF THE BODY IS AGAIN COVERED WITH A FURTHER INSULATING FILM WHICH IS THINNER THAN THAT OF THE REMAINING INSULATING FILM, AND THEN A CONTROL ELECTRODE IS FORMED ON THE FURTHER INSULATING FILM.

3. 发明授权

US3895240A Set preferring R-S flip-flop circuit 失效
标题翻译：设置优先R-S触发器电路
公开(公告)号：US3895240A
公开(公告)日：1975-07-15
申请号：US43544374
申请日：1974-01-22
申请人： HITACHI LTD
发明人： KAWAGOE HIROTO
IPC分类号： H03K3/356 , H03K3/286 , H03K3/33
CPC分类号： H03K3/356017 , H03K3/356078
摘要： A set preferring R-S flip-flop circuit constructed of insulated gate field-effect transistors, which comprises a flip-flop body including first and second inverter circuits coupled in cross connection, and a set input transistor connected on the input side of the flip-flop body. A reset input transistor is included in the flip-flop body and is used as a part thereof, so that the number of necessary transistors is reduced.
摘要翻译：一种由绝缘栅场效应晶体管构成的优选的RS触发器电路，其包括触发器主体，其包括交叉耦合的第一和第二反相器电路以及连接在触发器的输入侧上的设置输入晶体管身体。复位输入晶体管被包括在触发器主体中并且被用作其一部分，使得必需的晶体管的数量减少。

4. 发明授权

US3892985A Set-preferring R-S flip-flop circuit 失效
标题翻译：设置优先R-S触发器电路
公开(公告)号：US3892985A
公开(公告)日：1975-07-01
申请号：US45019074
申请日：1974-03-11
申请人： HITACHI LTD
发明人： KAWAGOE HIROTO
IPC分类号： H03K3/356 , H03K3/286 , H03K3/33
CPC分类号： H03K3/356113
摘要： A set-preferring R-S flip-flop circuit comprises a first inverter circuit and a second inverter circuit. The first inverter circuit includes first, third and fifth MISFETs of a first conductivity type channel and second, fourth and sixth MISFETs of a second conductivity type channel. The first and third MISFETs are connected in parallel with each other and are connected between an output terminal of the first inverter circuit and a first power source terminal in series with the fifth MISFET. The sixth MISFET is connected between the output terminal and a second power source terminal, and the second and fourth MISFETs are connected between the output terminal and the second power source terminal in series with each other. The second inverter circuit includes a seventh MISFET of the first conductivity type channel connected between an output terminal of the second inverter circuit and the first power source terminal, and an eighth MISFET of the second conductivity type channel connected between the output terminal and the second power source terminal. An output signal of the first inverter circuit is transferred to input electrodes of the seventh and eighth MISFETs. An output signal of the second inverter circuit is fed back to input electrodes of the first and second MISFETs. A reset signal is applied to input electrodes of the third and fourth MISFETs. A set signal is applied to input electrodes of the fifth and sixth MISFETs.
摘要翻译：优先选择的R-S触发器电路包括第一反相器电路和第二反相器电路。第一逆变器电路包括第一导电类型沟道的第一，第三和第五MISFET以及第二导电类型沟道的第二，第四和第六MISFET。第一和第三MISFET彼此并联连接，并且连接在第一反相器电路的输出端和与第五MISFET串联的第一电源端。第六MISFET连接在输出端子和第二电源端子之间，第二和第四MISFET彼此串联连接在输出端子和第二电源端子之间。第二逆变器电路包括连接在第二逆变器电路的输出端子和第一电源端子之间的第一导电型沟道的第七MISFET和连接在输出端子与第二电力之间的第二导电型沟道的第八MISFET 源码终端。第一反相器电路的输出信号被传送到第七和第八MISFET的输入电极。第二反相器电路的输出信号被反馈到第一和第二MISFET的输入电极。复位信号施加到第三和第四MISFET的输入电极。设置信号施加到第五和第六MISFET的输入电极。

5. 发明授权

US3909306A MIS type semiconductor device having high operating voltage and manufacturing method 失效
标题翻译：具有高工作电压的MIS型半导体器件和制造方法
公开(公告)号：US3909306A
公开(公告)日：1975-09-30
申请号：US44035674
申请日：1974-02-07
申请人： HITACHI LTD
发明人： SAKAMOTO TAKASHI , TSUJI NOBUHIRO , KAWAGOE HIROTO
IPC分类号： H01L21/00 , H01L21/336 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7835 , H01L21/00 , H01L29/78 , Y10S148/043 , Y10S148/053
摘要： A semiconductor device of metal-insulator-semiconductor construction and having a high operating voltage is formed of a semi-conductor substrate of one conductivity type which has a drain region of the opposite conductivity type and low impurity concentration formed in its major surface. The low impurity concentration region has formed therein a region of opposite conductivity type of a high impurity concentration. Simultaneously with the formation the high impurity concentration region, a source region of opposite conductivity type and high impurity concentration is formed in the substrate. An insulated gate electrode is formed to bridge the source region and the drain region of low impurity concentration, but to be spaced from the region of the high impurity concentration in the drain region, so that a depletion or space charge region extends deeply into the drain region.
摘要翻译：金属 - 绝缘体 - 半导体结构的半导体器件具有高的工作电压由一种导电类型的半导体衬底形成，其具有相反导电类型的漏极区域和在其主表面上形成的低杂质浓度。低杂质浓度区域中形成了杂质浓度高的相反导电型区域。在形成高杂质浓度区域的同时，在衬底中形成具有相反导电类型和高杂质浓度的源极区域。形成绝缘栅电极以桥接低杂质浓度的源极区域和漏极区域，但是与漏极区域中的高杂质浓度区域隔开，使得耗尽区域或空间电荷区域深深延伸到漏极地区。

6. 发明授权

US3870897A Digital circuit 失效
标题翻译：数字电路
公开(公告)号：US3870897A
公开(公告)日：1975-03-11
申请号：US33252273
申请日：1973-02-14
申请人： HITACHI LTD
发明人： HATSUKANO YOSHIKAZU , NOMIYA KOSEI , KAWAGOE HIROTO
IPC分类号： G09G3/04 , H03K19/017 , H03K19/096 , H03K19/08 , G11C11/34 , H03K19/36
CPC分类号： H03K19/017 , G09G3/04 , H03K19/096
摘要： A digital circuit has a memory circuit and a logical circuit connected in cascade between first and second delay circuits. The first delay circuit controls an input signal to the digital circuit, so that the delay of the input signal due to a stage or stages preceding to the digital circuit may fall within a delay by the first delay circuit, and the second delay circuit controls an output signal from the digital circuit, so that delays due to the memory and logical circuits may fall within a delay by the second delay circuit, whereby the output signal is made apparently free from the delays due to the preceding stage or stages and to the memory and logical circuits.
摘要翻译：数字电路具有在第一和第二延迟电路之间级联连接的存储器电路和逻辑电路。第一延迟电路控制到数字电路的输入信号，使得由数字电路之前的级或级引起的输入信号的延迟可能由第一延迟电路落在延迟范围内，并且第二延迟电路控制来自数字电路的输出信号，使得由于存储器和逻辑电路引起的延迟可能由第二延迟电路落在延迟之内，由此使得输出信号明显地没有由于前一级或级的延迟和存储器和逻辑电路。

7. 发明授权

US3590340A Breakdown preventing circuit and an integrated device thereof for a semiconductor device having an insulate gate electrode 失效
标题翻译：具有绝缘栅极电极的半导体器件的断路保护电路及其集成器件
公开(公告)号：US3590340A
公开(公告)日：1971-06-29
申请号：US3590340D
申请日：1968-02-23
申请人： HITACHI LTD
发明人： KUBO MASAHARU , KAWAGOE HIROTO , FURUYA TERUO , HATSUKANO YOSHIKAZU
IPC分类号： H01L23/522 , H01L27/02 , H01L27/06 , H01L19/00 , H01C7/14
CPC分类号： H01L27/0629 , H01L23/522 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： A circuit and an integration thereof for preventing the breakdown of an oxide film in an MOS type field effect transistor, wherein a resistor is connected between a metal gate electrode and a protecting diode (clamp diode).

8. 发明专利

DE2417994A1 未知
公开(公告)号：DE2417994A1
公开(公告)日：1975-07-24
申请号：DE2417994
申请日：1974-04-11
申请人： HITACHI LTD
发明人： KAWAGOE HIROTO , NOMIYA KOSEI
IPC分类号： H03K3/354 , H03F1/30 , H03F3/345 , H03K3/011 , H03L1/00 , H01L23/56 , G05F1/62 , H03K1/02

9. 发明专利

DE2404184A1 未知
公开(公告)号：DE2404184A1
公开(公告)日：1974-08-08
申请号：DE2404184
申请日：1974-01-29
申请人： HITACHI LTD
发明人： SAKAMOTO TAKASHI , TSUJI NOBUHIRO , KAWAGOE HIROTO
IPC分类号： H01L21/00 , H01L21/336 , H01L29/78 , H01L11/14
摘要： A semiconductor device of metal-insulator-semiconductor construction and having a high operating voltage is formed of a semi-conductor substrate of one conductivity type which has a drain region of the opposite conductivity type and low impurity concentration formed in its major surface. The low impurity concentration region has formed therein a region of opposite conductivity type of a high impurity concentration. Simultaneously with the formation the high impurity concentration region, a source region of opposite conductivity type and high impurity concentration is formed in the substrate. An insulated gate electrode is formed to bridge the source region and the drain region of low impurity concentration, but to be spaced from the region of the high impurity concentration in the drain region, so that a depletion or space charge region extends deeply into the drain region.

10. 发明专利

DE2315202A1 未知
公开(公告)号：DE2315202A1
公开(公告)日：1973-10-04
申请号：DE2315202
申请日：1973-03-27
申请人： HITACHI LTD
发明人： NOMIYA KOSEI , KAWAGOE HIROTO
IPC分类号： G11C19/28 , H03K3/356 , H03K3/286

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